M24SR04-Y Datasheet, PDF (71/90 Pages) STMicroelectronics – Support of NDEF data structure

M24SR04-Y M24SR04-G
I2C DC and AC parameters
Table 79. I²C AC characteristics (1 MHz)
Test conditions specified in Table 74
(preliminary data based on design simulations)
Symbol Alt.
Parameter
Min.
Max. Unit
f_C
t_CHCL ⁽¹⁾
t_CLCH ⁽²⁾
t_XH1XH2
t_XL1XL2
t_DL1DL2
t_DXCX
t_CLDX
t_CLQX
t_CLQV ⁽⁴⁾⁽⁵⁾
t_CHDX ⁽⁶⁾
t_DLCL
t_CHDH
t_DHDL
f_SCL
t_HIGH
t_LOW
t_R
t_F
t_F
t_SU:DAT
t_HD:DAT
t_DH
t_AA
t_SU:STA
t_HD:STA
t_SU:STO
t_BUF
Clock frequency
Clock pulse width high
Clock pulse width low
Input signal rise time
Input signal fall time
SDA (out) fall time
Data in set up time
Data in hold time
Data out hold time
Clock low to next data valid (access time)
Start condition set up time
Start condition hold time
Stop condition set up time
Time between Stop condition and next Start
condition
I²C write time in one page
t_W
t_{WR I²C write time up to 246 bytes}
t_NS ⁽⁷⁾
-
Pulse width ignored (input filter on SCL and
SDA)
0.05
260
500
(3)
(3)
20
50
0
100
-
250
250
250
500
-
-
-
1000 kHz
-
ns
-
ns
(3)
ns
(3)
ns
120
ns
-
ns
-
ns
-
ns
450
ns
-
ns
-
ns
-
ns
-
ns
5
ms
150
ms
80
ns
1. t_CHCL timeout.
2. t_CLCH timeout.
3. There is no min. or max. value for the input signal rise and fall times. It is however recommended by the I²C
specification that the input signal rise and fall times be less than 120 ns when f_C < 1 MHz.
4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
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6. For a reStart condition, or following a write cycle.
7. Characterized only, not tested in production.
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