M24SR04-Y Datasheet, PDF (53/90 Pages) STMicroelectronics – Support of NDEF data structure

M24SR04-Y M24SR04-G
I²C and RF command sets
Name
Byte field
Bit field
Instruction code
FSDI
DID (0 ≤ DID ≤ 14)
2 CRC bytes
Table 59. RATS command
INS
Param
0xE0
1 byte
b7-b4
b3-b0
CRC
2 bytes
The FSDI field codes the FSD that defines the maximum size that an RF or I²C host is able
to receive. Table 60 gives the conversion from FDSI to FSD.
Table 60. Conversion from FDSI to FSD
FSDI 0x0
0x1
0x2
0x3
0x4
0x5 0x6 0x7 0x8
0x9h-
0xE
0xF
FSD
16
24
32
40
48
64 96 128 256 RFU
256
The DID field defines the value of the addressed M24SR04.
Name
TL
Table 61. ATS response
T0
TA(1)
TB(1)
Byte field
0x05
0x78
1 byte
Bit field
Length of the ATS
response
FSCI = 256 bytes
The maximum ascending data rate is 106 kbps
The maximum descending data rate is 106 kbps
FWI field (9.6 ms when TB = 0x50)
SFGI field (302 µs when TB = 0x50)
The DID is supported
2 CRC bytes
1 byte
b8-b5
b4-b1
TC(1)
0x02
CRC
2 bytes
The FSCI codes the FSC which stands for the maximum frame size that the M24SR04 is
able to receive. The M24SR04 is able to receive up to 256 bytes of command. If the RF or
I²C host sends a command with more than 256 bytes, the M24SR04 will not be able to treat
the command and will not reply.
The FWI which stands for the Frame Waiting time Integer codes the FWT. This time
corresponds to the maximum duration while an RF or I²C host shall send before sending the
next command.
DocID024754 Rev 15
53/90
78