ST72561XX Datasheet, PDF (70/324 Pages) STMicroelectronics – Clock, reset and supply management

Power saving modes
ST72561-Auto
Figure 30. AWUF halt timing diagram
t_AWU
RUN MODE
HALT MODE
f_CPU
f_{AWU_RC}
AWUFH interrupt
256 or 4096 t_CPU
RUN MODE
Clear
by software
Figure 31. AWUFH mode flow-chart
HALT INSTRUCTION
(MCCSR.OIE=0)
(AWUCSR.AWUEN=1)
WDGHALT ¹⁾
1
WATCHDOG
RESET
ENABLE
0
WATCHDOG
DISABLE
AWU RC OSC ON
MAIN OSC
OFF
PERIPHERALS ²⁾ OFF
CPU
OFF
I[1:0] BITS
10
N
RESET
N
Y
INTERRUPT ³⁾
AWU RC OSC OFF
Y
MAIN OSC
ON
PERIPHERALS OFF
CPU
ON
I[1:0] BITS
XX ⁴⁾
256 OR 4096 CPU CLOCK
CYCLE DELAY
AWU RC OSC
MAIN OSC
PERIPHERALS
CPU
I[1:0] BITS
OFF
ON
ON
ON
XX ⁴⁾
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note: 1 WDGHALT is an option bit. See option byte section for more details.
2 Peripheral clocked with an external clock source can still be active.
3 Only an AWUFH interrupt and some specific interrupts can exit the MCU from HALT mode
(such as external interrupt). Refer to Table 16 for more details.
4 Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the
CC register are set to the current software priority level of the interrupt routine and
recovered when the CC register is popped.
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Doc ID 12370 Rev 8