ST72561XX Datasheet, PDF (120/324 Pages) STMicroelectronics – Clock, reset and supply management

16-bit timer
ST72561-Auto
Bit 5 = OPM One Pulse Mode.
0: One Pulse mode is not active.
1: One Pulse mode is active, the ICAP1 pin can be used to trigger one pulse on the
OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated
pulse depends on the contents of the OC1R register.
Bit 4 = PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the
length of the pulse depends on the value of OC1R register; the period depends on the
value of OC2R register.
Bit 3, 2 = CC[1:0] Clock Control.
The timer clock mode depends on these bits:
Table 50. Clock control bits
Timer clock
f_CPU / 4
f_CPU / 2
f_CPU / 8
External Clock (where available)
CC1
0
1
CC0
0
1
0
1
Note:
12.7.3
If the external clock pin is not available, programming the external clock configuration stops
the counter.
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = EXEDG External Clock Edge.
This bit determines which type of level transition on the external clock pin EXTCLK will
trigger the counter register.
0: a falling edge triggers the counter register.
1: a rising edge triggers the counter register.
Control/status register (CSR)
Read/ write (bits 7:3 read only)
Reset value: xxxx x0xx (xxh)
7
ICF1
OCF1
TOF
ICF2
0
OCF2
TIMD
0
0
Bit 7 = ICF1 Input Capture Flag 1.
0: no input capture (reset value).
1: an input capture has occurred on the ICAP1 pin or the counter has reached the
OC2R value in PWM mode. To clear this bit, first read the SR register, then read or
write the low byte of the IC1R (IC1LR) register.
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Doc ID 12370 Rev 8