ST72561XX Datasheet, PDF (165/324 Pages) STMicroelectronics – Clock, reset and supply management

ST72561-Auto
LINSCI serial communication interface (LIN master/slave)
Note:
15.5.6
Note:
with:
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
TR = 1, 2, 4, 8, 16, 32, 64,128
(see SCT[2:0] bits)
RR = 1, 2, 4, 8, 16, 32, 64,128
(see SCR[2:0] bits)
All these bits are in the SCIBRR register.
Example 1: If f_CPU is 8 MHz (normal mode) and if PR = 13 and TR = RR = 1, the transmit
and receive baud rates are 38400 baud.
The baud rate registers MUST NOT be changed while the transmitter or the receiver is
enabled.
Extended baud rate generation
The extended prescaler option gives a very fine tuning on the baud rate, using a 255 value
prescaler, whereas the conventional baud rate generator retains industry standard software
compatibility.
The extended baud rate generator block diagram is described in Figure 79.
The output clock rate sent to the transmitter or to the receiver will be the output from the 16
divider divided by a factor ranging from 1 to 255 set in the SCIERPR or the SCIETPR
register.
The extended prescaler is activated by setting the SCIETPR or SCIERPR register to a value
other than zero. The baud rates are calculated as follows:
Tx =
f_CPU
Rx =
f_CPU
16_*ETPR*(PR*TR)
16_*ERPR*(PR*RR)
with:
ETPR = 1...255 (see SCIETPR register)
ERPR = 1...255 (see SCIERPR register)
Doc ID 12370 Rev 8
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