STEVAL-IME008V1 Datasheet, PDF (7/19 Pages) STMicroelectronics – Load simulator using signal equivalent circuits

STEVAL-IME008V1
Schematic diagrams
Figure 6. STEVAL-IME008V1 circuit schematic (6 of 16)
U4B
FPGA - Bank 1
F16
IO_1_L01N_A24_VREF _F15
IO_1_L01P_A25 _C18
IO_1_L29N_A22_M1A14 _C17
IO_1_L29P_A23_M1A13 _G14
IO_1_L30N_A20_M1A11 _F14
IO_1_L30P_A21_M1RESET _D18
IO_1_L31N_A18_M1A12 _D17
IO_1_L31P_A19_M1CKE _G13
IO_1_L32N_A16_M1A9 _H12
IO_1_L32P_A17_M1A8 _E18
IO_1_L33N_A14_M1A4 _E16
IO_1_L33P_A15_M1A10 _K13
IO_1_L34N_A12_M1BA2 _K12
IO_1_L34P_A13_M1WE _F18
IO_1_L35N_A10_M1A2 _F17
IO_1_L35P_A11_M1A7 _H14
IO_1_L36N_A8_M1BA1 _H13
IO_1_L36P_A9_M1BA0 _H16
IO_1_L37N_A6_M1A1 _H15
IO_1_L37P_A7_M1A0 _G18
IO_1_L38N_A4_M1CLKN _G16
IO_1_L38P_A5_M1CLK _K14
IO_1_L39N_M1ODT _J13
IO_1_L39P_M1A3 _L13
IO_1_L40N_GCLK10_M1A6 _L12
IO_1_L40P_GCLK11_M1A5 _K16
IO_1_L41N_GCLK8_M1CASN _K15
IO_1_L41P_GCLK9_IRDY1_M1RASN _L16
IO_1_L42N_GCLK6_TRDY1_M1LDM _L15
IO_1_L42P_GCLK7_M1UDM _H18
IO_1_L43N_GCLK4_M1DQ5 _H17
IO_1_L43P_GCLK5_M1DQ4 _J18
IO_1_L44N_A2_M1DQ7 _J16
IO_1_L44P_A3_M1DQ6 _K18
IO_1_L45N_A0_M1LDQSN _K17
IO_1_L45P_A1_M1LDQS _L18
IO_1_L46N_FOE_B_M1DQ3 _L17
IO_1_L46P_FCS_B_M1DQ2 _M18
IO_1_L47N_LDC_M1DQ1 _M16
IO_1_L47P_FWE_B_M1DQ0 _N18
IO_1_L48N_M1DQ9 _N17
IO_1_L48P_HDC_M1DQ8 _P18
IO_1_L49N_M1DQ11 _P17
IO_1_L49P_M1DQ10 _N16
IO_1_L50N_M1UDQSN _N15
IO_1_L50P_M1UDQS _T18
IO_1_L51N_M1DQ13 _T17
IO_1_L51P_M1DQ12 _U18
IO_1_L52N_M1DQ15 _U17
IO_1_L52P_M1DQ14 _N14
IO_1_L53N_VREF _M14
IO_1_L53P _M13
IO_1_L61N _L14
IO_1_L61P _P16
IO_1_L74N_DOUT_BUSY _P15
IO_1_L74P_AWAKE
FPGA_PMOD1_P2
FPGA_PMOD1_P1
FPGA_PMOD1_P4
FPGA_PMOD1_P3
FPGA_PMOD1_P8
FPGA_PMOD1_P7
FPGA_PMOD1_P10
FPGA_PMOD1_P9
FPGA_PMOD2_P2
FPGA_PMOD2_P1
FPGA_PMOD2_P4
FPGA_PMOD2_P3
FPGA_PMOD2_P8
FPGA_PMOD2_P7
FPGA_PMOD2_P10
FPGA_PMOD2_P9
CTRL_LED1
CTRL_LED0
SEL_PROG_PB
FPGA_CLK_66MHZ
START_PB
STOP_PB
FPGA USER I/O
FPGA_RESET
J7 ^{NOT ASSEMBLY}
FPGA_USER_IO_0
FPGA_USER_IO_1
FPGA_USER_IO_2
FPGA_USER_IO_3
FPGA_USER_IO_4
FPGA_USER_IO_5
FPGA_USER_IO_6
FPGA_USER_IO_7
FPGA_USER_IO_8
FPGA_USER_IO_9
FPGA_USER_IO_10
FPGA_USER_IO_11
FPGA_USER_IO_12
FPGA_USER_IO_13
FPGA_USER_IO_14
FPGA_USER_IO_15
CTRL_LED3
CTRL_LED2
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
28
27
30
29
32
31
HEADER 16X2
FPGA_DOUT_BUSY
FPGA_AWAKE
TP1
TEST POINT
FPGA_MCU_AWAKE
XC6SLX16-2CSG324C
GSPG30072014DI1205
DocID026791 Rev 1
7/19
19