STEVAL-IME008V1 Datasheet, PDF (11/19 Pages) STMicroelectronics – Load simulator using signal equivalent circuits

STEVAL-IME008V1
Schematic diagrams
Figure 10. STEVAL-IME008V1 circuit schematic (10 of 16)
FPGA CONFIGURATION
+VFPGA_IO_3V3
FPGA_INIT_B
FPGA_MODE0
FPGA_MODE1
R16
10K 0402
R17
2K43 0402
R21
2K43 0402 DNP
R18
2K43 0402 DNP
MCU_FPGA_INIT_B
MCU_FPGA_MODE1
R22
2K43 0402
Configuration mode selection:
FPGA_MODE0 = Parallel (Low) or Serial (High)
FPGA_MODE1 = Master (Low) or Slave (High)
When FPGA_INIT_B (bidirectional open-drain) is Low the configuration memory is
being cleared.
When held Low, the start of configuration is delayed.
During configuration, a Low on this output indicates that a configuration data
error has occurred.
SPI FLASH CTRL SIGNALS
Place R38 close to the FPGA device
R38 33R2 0402
CCLK
FPGA_SPI_MISO1
FPGA_SPI_MOSI
FPGA_SPI_SEL
FPGA_SPI_MISO2
FPGA_SPI_MISO3
TO CORRECT
J10
FPGA_SPI_CCLK
FPGA_SPI_MISO1
FPGA_SPI_MOSI
FPGA_SPI_SEL
FPGA_SPI_MISO2
FPGA_SPI_MISO3
MCU_FPGA_PROG
+VFPGA_IO_3V3
1
2
3
4
R39
5
NA 0402
6
7
8
9
10
CON10 R127
56
EXT SPI
FLASH
Place D29
close to J10
D29
GREEN
C33
10uF 10V 0805
C34
100nF
R40
NA 0402
C33 Details:
TDK (C2012X7R1A106K) - DIGIKEY (445-6857-2-ND)
Dimension 0805 - EIA 2012
DocID026791 Rev 1
GSPG30072014DI1230
11/19
19