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M36L0R7040T0 Datasheet, PDF (7/18 Pages) STMicroelectronics – 128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory and 16 Mbit PSRAM, 1.8V Supply, Multi-Chip Package
M36L0R7040T0, M36L0R7040B0
It is not allowed to set EF at VIL, E1P at VIL and E2P
at VIH at the same time.
PSRAM Write Enable (WP). The Write Enable
input controls writing to the PSRAM memory array.
WP is active low.
PSRAM Output Enable (GP). The Output En-
able gates the outputs through the data buffers
during a Read operation of the PSRAM memory.
GP is active low.
PSRAM Upper Byte Enable (UBP). The Upper
Byte Enable input enables the upper byte for
PSRAM (DQ8-DQ15). UBP is active low.
PSRAM Lower Byte Enable (LBP). The Lower
Byte Enable input enables the lower byte for
PSRAM (DQ0-DQ7). LBP is active low.
VDDF Supply Voltage. VDDF provides the power
supply to the internal cores of the Flash memory
component. It is the main power supply for all
Flash operations (Read, Program and Erase).
VDDP Supply Voltage. VDDP provides the power
supply to the internal core of the PSRAM device. It
is the main power supply for all PSRAM opera-
tions.
VDDQ Supply Voltage. VDDQ provides the power
supply for the Flash Memory I/O pins. This allows
all Outputs to be powered independently of the
Flash Memory core power supply, VDDF.
VPPF Program Supply Voltage. VPPF is both a
Flash control input and a Flash power supply pin.
The two functions are selected by the voltage
range applied to the pin.
If VPPF is kept in a low voltage range (0V to VDDQ)
VPPF is seen as a control input. In this case a volt-
age lower than VPPLKF gives an absolute protec-
tion against Program or Erase, while VPPF > VPP1F
enables these functions (see Tables 6 and 7, DC
Characteristics for the relevant values). VPPF is
only sampled at the beginning of a Program or
Erase; a change in its value after the operation has
started does not have any effect and Program or
Erase operations continue.
If VPPF is in the range of VPPHF it acts as a power
supply pin. In this condition VPPF must be stable
until the Program/Erase algorithm is completed.
VSS Ground. VSS is the common ground refer-
ence for all voltage measurements in the Flash
(core and I/O Buffers) and PSRAM chips.
Note: Each Flash memory device in a system
should have their supply voltage (VDDF) and
the program supply voltage VPPF decoupled
with a 0.1µF ceramic capacitor close to the pin
(high frequency, inherently low inductance ca-
pacitors should be as close as possible to the
package). See Figure 6., AC Measurement
Load Circuit. The PCB track widths should be
sufficient to carry the required VPPF program
and erase currents.
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