M36L0R7040T0 Datasheet, PDF (4/18 Pages) STMicroelectronics – 128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory and 16 Mbit PSRAM, 1.8V Supply, Multi-Chip Package

M36L0R7040T0, M36L0R7040B0
SUMMARY DESCRIPTION
The M36L0R7040T0 and M36L0R7040B0 com-
bine two memory devices in a Multi-Chip Package:
a 128-Mbit, Multiple Bank Flash memory, the
M30L0R7000T0 or M30L0R7000B0, and a 16-
Mbit PseudoSRAM, the M69AR024B. Recom-
mended operating conditions do not allow more
than one memory to be active at the same time.
The memory is offered in a Stacked TFBGA88
(8x10mm, 8x10 ball array, 0.8mm pitch) package.
In addition to the standard version, the packages
are also available in Lead-free version, in compli-
ance with JEDEC Std J-STD-020B, the ST ECO-
PACK 7191395 Specification, and the RoHS
(Restriction of Hazardous Substances) directive.
All packages are compliant with Lead-free solder-
ing processes.
The memory is supplied with all the bits erased
(set to ‘1’).
Figure 2. Logic Diagram
V_DDQ V_PPF
V_DDF
V_DDP
23
A0-A22
E_F
G_F
W_F
RP_F
WP_F
L_F
K_F
16
DQ0-DQ15
WAIT_F
M36L0R7040T0
M36L0R7040B0
E1_P
G_P
W_P
E2_P
UB_P
LB_P
Table 1. Signal Names
A0-A22 ⁽¹⁾
Address Inputs
DQ0-DQ15 Common Data Input/Output
V_DDF
Power Supply for Flash Memory
V_DDQ
Flash Memory Power Supply for I/O
Buffers
V_PPF
Flash Optional Supply Voltage for Fast
Program and Erase
V_SS
Ground
V_DDP
PSRAM Power Supply
NC
Not Connected Internally
DU
Do Not Use as Internally Connected
Flash Memory Control Functions
L_F
Latch Enable Input
E_F
Chip Enable Input
G_F
Output Enable Input
W_F
Write Enable Input
RP_F
Reset Input
WP_F
Write Protect Input
K_F
Burst Clock
WAIT_F
Wait Data in Burst Mode
PSRAM Control Functions
E1_P
Chip Enable Input
G_P
Output Enable Input
W_P
Write Enable Input
E2_P
Power-down Input
UB_P
Upper Byte Enable Input
LB_P
Lower Byte Enable Input
Note: 1. A22-A20 are not connected to the PSRAM component.
VSS
AI08467
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