STM32F411XC Datasheet, PDF (65/149 Pages) STMicroelectronics – Clock, reset and supply management

STM32F411xC STM32F411xE
Electrical characteristics
Table 16. VCAP_1/VCAP_2 operating conditions⁽¹⁾
Symbol
Parameter
Conditions
CEXT
ESR
Capacitance of external capacitor with a single VCAP
pin available
ESR of external capacitor with a single VCAP pin
available
4.7 µF
<1Ω
1. When bypassing the voltage regulator, the two 2.2 µF V_CAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
6.3.3
6.3.4
Operating conditions at power-up/power-down (regulator ON)
Subject to general operating conditions for T_A.
Table 17. Operating conditions at power-up / power-down (regulator ON)
Symbol
Parameter
Min
Max
Unit
t_VDD
V_DD rise time rate
V_DD fall time rate
20
∞
µs/V
20
∞
Operating conditions at power-up / power-down (regulator OFF)
Subject to general operating conditions for T_A.
Table 18. Operating conditions at power-up / power-down (regulator OFF)⁽¹⁾
Symbol
Parameter
Conditions
Min Max Unit
t_VDD
t_VCAP
V_DD rise time rate
V_DD fall time rate
V_{CAP_1} and V_{CAP_2} rise time rate
V_{CAP_1} and V_{CAP_2} fall time rate
Power-up
Power-down
Power-up
Power-down
20
∞
20
∞
µs/V
20
∞
20
∞
1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when V_DD reach below
1.08 V.
Note:
This feature is only available for UFBGA100 package.
DocID026289 Rev 6
65/149
123