 English |
|
|
|
|
|
|
|
| STM32F411XC Datasheet, PDF (103/149 Pages) STMicroelectronics – Clock, reset and supply management | |||
| |||
| ◁ |
STM32F411xC STM32F411xE
Electrical characteristics
6.3.17
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 53).
Unless otherwise specified, the parameters given in Table 56 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 14. Refer to Table 53: I/O static characteristics for the values of VIH and VIL for
NRST pin.
Table 56. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RPU
Weak pull-up equivalent
resistor(1)
VIN = VSS
30
40
50
kΩ
VF(NRST)(2) NRST Input filtered pulse
-
-
100
ns
VNF(NRST)(2) NRST Input not filtered pulse
VDD > 2.7 V
300
-
-
ns
TNRST_OUT Generated reset pulse duration
Internal Reset
source
20
-
-
µs
1. Trehseisptaunllc-uepmisusdtebseigmneindimwuithma(~tr1u0e%reosridsetarn).ce in series with a switchable PMOS. This PMOS contribution to the series
2. Guaranteed by design.
Figure 32. Recommended NRST pin protection
([WHUQDO
UHVHWFLUFXLW
9''
1567
538
Â)
,QWHUQDO5HVHW
)LOWHU
670)
DLF
1. The reset network protects the device against parasitic resets.
2.
The user must ensure that the level
Table 56. Otherwise the reset is not
on the NRST pin can go below the
taken into account by the device.
VIL(NRST)
max
level
specified
in
DocID026289 Rev 6
103/149
123
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese