ADS6445 Datasheet, PDF (65/75 Pages) STMicroelectronics – QUAD CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS

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ADS6445, ADS6444
ADS6443, ADS6442
SLAS531 – MAY 2007
OUTPUT TIMINGS AT LOWER SAMPLING FREQUENCIES
Setup, hold, and other timing parameters are specified across sampling frequencies and for each type of output
interface in the following tables.
Table 28 to Table 31: Typical values are at 25°C, min and max values are across the full temperature range
T_MIN = –40°C to T_MAX = 85°C, AVDD = LVDD = 3.3 V, C_L = 5 pF, I_O = 3.5 mA, R_L = 100 Ω, no internal
termination, unless otherwise noted.
Timing parameters are ensured by design and characterization and not tested in production.
Ts = 1/ Sampling frequency = 1/Fs
Table 27. Clock Propagation Delay for Different Interface Options
INTERFACE
1-Wire with DDR bit clock
SERIALIZATION
14x
16x
2-Wire with DDR bit clock
14x
2-Wire with SDR bit clock
2-Wire with DDR bit clock
16x
2-Wire with SDR bit clock
CLOCK PROPAGATION DELAY, t_{pd_clk}
t_{pd_clk} = 0.428xT_s + t_delay
t_{pd_clk} = 0.375xT_s + t_delay
t_{pd_clk} = 0.857xT_s + t_delay
t_{pd_clk} = 0.428xT_s + t_delay
t_{pd_clk} = 0.75xT_s + t_delay
t_{pd_clk} = 0.375xT_s + t_delay
SERIALIZER LATENCY ⁽¹⁾
clock cycles
0
2
(when t_{pd_clk} ≥ T_s)
1
(when t_{pd_clk} < T_s)
0
1
(when t_{pd_clk} ≥ T_s)
0
(when t_{pd_clk} < T_s)
0
(1) Note that the total latency = ADC latency + internal serializer latency. The ADC latency is 12 clock cycles.
SAMPLING
SERIALIZATION FREQUENCY
MSPS
65
40
14×
20
10
65
16×
Table 28. Timings for 1-Wire Interface
DATA SETUP TIME, t_su
ns
MIN
TYP
MAX
0.3
0.5
0.65
0.85
1.3
1.65
3.2
3.5
DATA HOLD TIME, t_h
ns
MIN
TYP
MAX
0.4
0.6
0.7
0.9
1.6
1.9
3.2
3.6
0.22
0.42
0.35
0.55
t_delay
ns
MIN
TYP
F_s ≥ 40 MSPS
3
4
F_s < 40 MSPS
3
4.5
F_s ≥ 40 MSPS
3
4
F_s < 40 MSPS
3
4.5
MAX
5
6
5
6
Table 29. Timings for 2-Wire Interface, DDR Bit Clock
SAMPLING
SERIALIZATION FREQUENCY
DATA SETUP TIME, t_su
ns
DATA HOLD TIME, t_h
ns
MSPS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
105
0.45
0.65
0.5
0.7
92
0.55
0.75
0.6
0.8
3.4
14×
80
0.65
0.85
0.7
0.9
65
0.8
1.1
0.8
1.1
40
1.4
1.7
1.5
1.9
3.7
105
0.35
0.55
0.4
0.6
92
0.45
0.65
0.5
0.7
3.4
16×
80
0.55
0.75
0.6
0.8
65
0.6
0.9
0.7
1
40
1.1
1.4
1.3
1.7
3.7
t_delay
ns
TYP
F_s ≥ 45 MSPS
4.4
F_s < 45 MSPS
5.2
F_s ≥ 45 MSPS
4.4
F_s < 45 MSPS
5.2
MAX
5.4
6.7
5.4
6.7
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