RM0383 Datasheet, PDF (585/837 Pages) STMicroelectronics – This Reference manual targets application developers

RM0383
Serial peripheral interface (SPI)
It will be: I²S bitrate = 32 x 2 x F_S if the packet length is 32-bit wide.
Figure 227. Audio sampling frequency definition
16-bit or 32-bit Left channel _{16-bit or 32-bit Right channel}
sampling point
32-bits or 64-bits
F_S
F_S: Audio sampling frequency
sampling point
When the master mode is configured, a specific action needs to be taken to properly
program the linear divider in order to communicate with the desired audio frequency.
Figure 228. I²S clock generator architecture
MCK
I2SxCLK
8-bit Linear
Divider +
reshaping stage
Divider by 4
0
CK
Div2
0
1
1
MCKOE
MCKOE ODD
I2SDIV[7:0]
I2SMOD
CHLEN
Note:
1. Where x could be 2 or 3.
Figure 227 presents the communication clock architecture. To achieve high-quality audio
performance, the I2SxCLK clock source can be either the PLLI2S output (through R division
factor) or an external clock (mapped to I2S_CKIN pin).
The audio sampling frequency can be 192 kHz, 96 kHz, or 48 kHz. In order to reach the
desired frequency, the linear divider needs to be programmed according to the formulas
below:
When the master clock is generated (MCKOE in the SPI_I2SPR register is set):
F_S = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD)*8)] when the channel frame is 16-bit wide
F_S = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD)*4)] when the channel frame is 32-bit wide
When the master clock is disabled (MCKOE bit cleared):
F_S = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD))] when the channel frame is 16-bit wide
F_S = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD))] when the channel frame is 32-bit wide
Table 89 provides example precision values for different clock configurations.
Other configurations are possible that allow optimum clock precision.
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