RM0377 Datasheet, PDF (503/862 Pages) STMicroelectronics – This reference manual targets application developers

Low-power timer (LPTIM)
RM0377
19.6.6 LPTIM Compare Register (LPTIMx_CMP)
Address offset: 0x14
Reset value: 0x0000 0000
31
Res.
30
Res.
29
Res.
28
Res.
27
Res.
26
Res.
25
Res.
24
Res.
23
Res.
22
Res.
21
Res.
20
Res.
19
Res.
18
Res.
17
Res.
16
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CMP[15:0]
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 CMP: Compare value.
CMP is the compare value used by the LPTIM.
The LPTIMx_CMP register’s content must only be modified when the LPTIM is enabled (ENABLE bit is
set to ‘1’).
19.6.7 LPTIM Autoreload Register (LPTIMx_ARR)
Address offset: 0x18
Reset value: 0x0000 0001
31
Res.
30
Res.
29
Res.
28
Res.
27
Res.
26
Res.
25
Res.
24
Res.
23
Res.
22
Res.
21
Res.
20
Res.
19
Res.
18
Res.
17
Res.
16
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ARR[15:0]
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 ARR: Auto reload value.
ARR is the autoreload value for the LPTIM.
This value must be strictly greater than the CMP[15:0] value.
The LPTIMx_ARR register’s content must only be modified when the LPTIM is enabled (ENABLE bit is
set to ‘1’).
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