RM0377 Datasheet, PDF (337/862 Pages) STMicroelectronics – This reference manual targets application developers

Advanced encryption standard hardware accelerator (AES)
RM0377
Figure 63. 128-bit block construction according to the data type (continued)
$!4!490% B"ITSWAPPING
!%3?$).2OR!%3?$/542
-3"
7/2$
7/2$
BIT BIT BIT
  _
BIT BIT
 
BIT BIT BIT
  
BIT BIT
 
7/2$
BIT BIT BIT
  
BIT BIT
 
,3"
7/2$
BIT BIT BIT
  
BIT BIT

-3"
!%3PROCESSORINPUTOR!%3PROCESSOROUTPUT
,3"
-36
15.7
15.7.1
Operating modes
Mode 1: encryption
1. Disable the AES by resetting bit the EN bit in the AES_CR register.
2. Configure the Mode 1 by programming MODE[1:0]=00 in the AES_CR register and
select which type of chaining mode needs to be performed by programming the
CHMOD[1:0] bits.
3. Write the AES_KEYRx registers (128-bit encryption key) and the AES_IVRx registers if
CTR or CBC mode is selected. For EBC mode, the AES_IVRx register is not used.
4. Enable the AES by setting the EN bit in the AES_CR register.
5. Write the AES_DINR register 4 times to input the plain text (MSB first) as shown in
Figure 64: Mode 1: encryption on page 337.
6. Wait until the CCF flag is set in the AES_SR register.
7. Reads the AES_DOUTR register 4 times to get the cipher text (MSB first) as shown in
Figure 64: Mode 1: encryption on page 337.
8. Repeat steps 5,6,7 to process all the blocks with the same encryption key.
72 72
04 04
-3"
Figure 64. Mode 1: encryption
72 72
04 04
,3"
7!)45.4),
FLAG##&
2$ _2$
#4 _#4
-3"
2$ 2$
#4 #4
,3"
).0540(!3%
72)4%/0%2!4)/.3
).4/!%3?$).;=
040,!).4%847ORDS0404
#4#90(%24%847ORDS#4#4
#/-054!4)/.0(!3%
/540540(!3%
2%!$/0%2!4)/.3
/&!%3?$/54;=
-36
337/862
DocID025942 Rev 2