PSD4235G2 Datasheet, PDF (50/89 Pages) STMicroelectronics – Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply

PSD4235G2
I/O PORTS
There are seven programmable I/O ports: Ports A,
B, C, D, E, F and G. Each port pin is individually
user configurable, thus allowing multiple functions
per port. The ports are configured using PSDsoft
Express or by the MCU writing to on-chip registers
in the CSIOP space.
The topics discussed in this section are:
s General Port architecture
s Port operating modes
s Port Configuration Registers (PCR)
s Port Data Registers
s Individual Port functionality.
General Port Architecture. The general archi-
tecture of the I/O Port block is shown in Figure 27.
Individual Port architectures are shown in Figure
29 to Figure 31. In general, once the purpose for a
port pin has been defined, that pin is no longer
Figure 27. General I/O Port Architecture
available for other purposes. Exceptions are not-
ed.
As shown in Figure 27, the ports contain an output
multiplexer whose select signals are driven by the
configuration bits in the Control Registers (Ports E,
F and G only) and PSDsoft Express Configuration.
Inputs to the multiplexer include the following:
s Output data from the Data Out register
s Latched address outputs
s CPLD Macrocell output
s External Chip Select from the CPLD.
The Port Data Buffer (PDB) is a tri-state buffer that
allows only one source at a time to be read. The
Port Data Buffer (PDB) is connected to the Internal
Data Bus for feedback and can be read by the
MCU. The Data Out and Macrocell outputs, Direc-
tion Register and Control Register, and port pin in-
put are all connected to the Port Data Buffer
(PDB).
DATA OUT
REG.
DQ
WR
ADDRESS
ALE
DQ
G
MACROCELL OUTPUTS
EXT CS
READ MUX
P
D
DATA IN
B
CONTROL REG.
DQ
WR
DIR REG.
DQ
WR
ENABLE PRODUCT TERM (.OE)
CPLD - INPUT
DATA OUT
ADDRESS
OUTPUT
MUX
OUTPUT
SELECT
ENABLE OUT
INPUT
MACROCELL
PORT PIN
AI02885
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