PSD4235G2 Datasheet, PDF (12/89 Pages) STMicroelectronics – Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply

PSD4235G2
Pin Name Pin Type
Description
PA0-PA7
51-58
I/O
CMOS
or
Open
Drain
These pins make up Port A. These port pins are configurable and can have the
following functions:
1. MCU I/O – standard output or input port.
2. CPLD Macrocell (McellA0-McellA7) outputs.
3. Latched, transparent or registered PLD inputs (can also be PLD input for address
A16 and above).
PB0-PB7
61-68
I/O
CMOS
or
Open
Drain
These pins make up Port B. These port pins are configurable and can have the
following functions:
1. MCU I/O – standard output or input port.
2. CPLD Macrocell (McellB0-McellB7) outputs.
3. Latched, transparent or registered PLD inputs (can also be PLD input for address
A16 and above).
PC0-PC7
41-48
I/O
CMOS
or
Slew
Rate
These pins make up Port C. These port pins are configurable and can have the
following functions:
1. MCU I/O – standard output or input port.
2. External Chip Select (ECS0-ECS7) outputs.
3. Latched, transparent or registered PLD inputs (can also be PLD input for address
A16 and above).
PD0
I/O
PD0 pin of Port D. This port pin can be configured to have the following functions:
CMOS 1. ALE/AS input – latches address on ADIO0-ADIO15.
79
or
2. AS input – latches address on ADIO0-ADIO15 on the rising edge.
Open 3. MCU I/O – standard output or input port.
Drain 4. Transparent PLD input (can also be PLD input for address A16 and above).
PD1
I/O
PD1 pin of Port D. This port pin can be configured to have the following functions:
CMOS 1. MCU I/O – standard output or input port.
80
or
2. Transparent PLD input (can also be PLD input for address A16 and above).
Open 3. CLKIN – clock input to the CPLD Macrocells, the APD Unit’s Power-down counter,
Drain and the CPLD AND Array.
PD2
1
I/O
CMOS
or
Open
Drain
PD2 pin of Port D. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Transparent PLD input (can also be PLD input for address A16 and above).
3. PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory and
I/O. When High, the PSD memory blocks are disabled to conserve power. The falling
edge of this signal can be used to get the device out of Power-down mode.
PD3
2
I/O
CMOS
or
Open
Drain
PD3 pin of Port D. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Transparent PLD input (can also be PLD input for address A16 and above).
3. WRH – for 16-bit data bus, write to high byte, active low.
PE0
71
I/O
CMOS
or
Open
Drain
PE0 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. TMS Input for the JTAG Serial Interface.
PE1
72
I/O
CMOS
or
Open
Drain
PE1 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. TCK Input for the JTAG Serial Interface.
PE2
73
I/O
CMOS
or
Open
Drain
PE2 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. TDI input for the JTAG Serial Interface.
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