PSD4235G2 Datasheet, PDF (1/89 Pages) STMicroelectronics – Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply

PSD4235G2
Flash In-System Programmable (ISP) Peripherals
For 16-bit MCUs (5V Supply)
PRELIMINARY DATA
FEATURES SUMMARY
PSD provides an integrated solution to 16-bit MCU
based applications that includes configurable
memories, PLD logic and I/O:
s Dual Bank Flash Memories
– 4 Mbit of Primary Flash Memory (8 uniform
sectors, 32K x 16)
– 256 Kbit Secondary Flash Memory with 4
sectors
– Concurrent operation: read from one memory
while erasing and writing the other
s 64 Kbit SRAM (Battery Backed)
s PLD with macrocells
– Over 3000 Gates of PLD: CPLD and DPLD
– CPLD with 16 Output Macrocells (OMCs) and
24 Input Macrocells (IMCs)
– DPLD – user defined internal chip select de-
coding
s Seven l/O Ports with 52 I/O pins
– 52 individually configurable I/O port pins that
can be used for the following functions:
– MCU I/Os
– PLD I/Os
– Latched MCU address output
– Special function l/Os
– l/O ports may be configured as open-drain
outputs
s In-System Programming (ISP) with JTAG
– Built-in JTAG compliant serial port allows full-
chip In-System Programmability
– Efficient manufacturing allow easy product
testing and programming
– Use low cost FlashLINK cable with PC
s Page Register
– Internal page register that can be used to ex-
pand the microcontroller address space by a
factor of 256
s Programmable power management
s High Endurance:
– 100,000 Erase/Write Cycles of Flash Memory
– 1,000 EraseWrite Cycles of PLD
– 15 Year Data Retention
s Single Supply Voltage
– 5V ±10%
s Memory Speed
– 70ns Flash memory and SRAM access time
Figure 1. Packages
TQFP80 (U)
December 2001
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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