ST92F120 Datasheet, PDF (46/320 Pages) STMicroelectronics – 8/16-BIT FLASH MCU FAMILY WITH RAM, EEPROM AND J1850 BLPD

ST92F120 - SINGLE VOLTAGE FLASH & EEPROM
FUNCTIONAL DESCRIPTION (Cont’d)
Table 9. Memory Structure for 36K Flash device
Sector
TestFlash (TF) (Reserved)
User OTP Area
Flash 0 (F0)
Flash 1 (F1)
Flash 2 (F2)
Flash 3 (F3)
Flash 4 / EEPROM 0 (F4/E0)
Flash 5 / EEPROM 1 (F5/E1)
Emulated EEPROM
Addresses
230000h to 230F7Fh
231F80h to 230FFFh
000000h to 000FFFh
010000h to 013FFFh
014000h to 015FFFh
016000h to 017FFFh
228000h to 2287FFh
22C000h to 22C7FFh
220000h to 2201FFh
Max Size
3968 bytes
128 bytes
4 Kbytes
16 Kbytes
8 Kbytes
8 Kbytes
2 Kbytes
2 Kbytes
512 bytes
3.2.3 Operation
The memory has a register interface mapped in
memory space (segment 22h). All operations are
enabled through the FCR (Flash Control Register)
ECR (EEPROM Control Register).
All operations on the Flash must be executed from
another memory (internal RAM, EEPROM, exter-
nal memory).
Flash (including TestFlash) and EEPROM have
duplicated sense amplifiers, so that one can be
read while the other is written. However simultane-
ous Flash and EEPROM write operations are for-
bidden.
An interrupt can be generated at the end of a
Flash or an EEPROM write operation: this inter-
rupt is multiplexed with an external interrupt EX-
TINTx (device dependent) to generate an interrupt
INTx.
The status of a write operation inside the Flash
and the EEPROM memories can be monitored
through the FESR[1:0] registers.
Control and Status registers are mapped in mem-
ory (segment 22h), as shown in the following fig-
ure.
Figure 24. Control and Status Register Map.
Register Interface
224000h
224001h
224002h
224003h
FCR
ECR
FESR0
FESR1
During a write operation, if the power supply drops
or the RESET pin is activated, the write operation
is immediately interrupted. In this case the user
must repeat the last write operation following pow-
er on or reset.
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