ST92F120 Datasheet, PDF (267/320 Pages) STMicroelectronics – 8/16-BIT FLASH MCU FAMILY WITH RAM, EEPROM AND J1850 BLPD

J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Bit 7:4 = MLC[3:0] Message Length Count.
Message Length Count bits 3 to 0 are written when
the program writes one of the IFR opcodes. Upon
detection of the EOD symbol which delineates the
body of a frame from the IFR portion of the frame,
the received byte counter is compared against the
count contained in MLC[3:0]. If they match, then
the IFR will be transmitted. If they do not match,
then the TRA bit in the ERROR register is set and
no transmit attempt occurs.
– While NFL=0, an MCL[3:0] decimal value be-
tween 1 and 11 is considered valid. MCL[3:0] val-
ues of 12, 13, 14, 15 are considered invalid and
will set the Transmit Request Aborted (TRA) bit
in the ERROR register.
– While NFL=1, an MCL[3:0] value between 1 and
15 is considered valid.
– For NFL=1 or 0, MCL[3:0] bits are don’t care dur-
ing a MSG or MSG+CRC opcode write.
– If writing an IFR opcode and MCL[3:0]=0000,
then the message length count check is ignored
(i.e. MLC=Count is disabled), and the IFR is en-
abled only on a correct CRC and a valid EOD
symbol assuming no other error conditions (IFD,
IBD, RBRK) appear.
Bit 3 = Reserved.
Bit 2:0 = OP[2:0] Transmit Opcode Select Bits.
The bits OP[2:0] form the code that the transmitter
uses to perform a transmit sequence. The codes
are listed in Table 50.
Table 50. Opcode definitions
OP[2:0] Transmit opcode
000
No operation or
Cancel
001 Send Break Symbol
Abbreviation
CANCEL
SBRK
MSG, Message Byte Opcode.
The Message byte opcode is set when the user
program wants to initiate or continue transmitting
the body of a message out the VPWO pin.
The body of a message is the string of data bytes
following an SOF symbol, but before the first EOD
symbol in a frame. If the J1850 bus is in an idle
condition when the opcode is written, an SOF
symbol is transmitted out the VPWO pin immedi-
ately before it transmits the data contained in TX-
DATA. If the JBLPD is not in idle and the J1850
transmitter has not been locked out by loss of arbi-
tration, then the TXDATA byte is transferred to the
serial output shift register for transmission immedi-
ately on completion of any previously transmitted
data. The final byte of a message string is not
transmitted using the MSG opcode (use the
MSG+CRC opcode).
Special Conditions for MSG Transmit:
– 1) A MSG cannot be queued on top of an execut-
ing IFR3 opcode. If so, then TRA is set, and
TDUF will get set because the transmit state ma-
chine will be expecting more data, then the in-
verted CRC is appended to this frame. Also, no
message byte will be sent on the next frame.
– 2) If NFL = 0 and an MSG queued without CRC
on Received Byte Count for this frame=10 will
trigger the TRA to get set, and TDUF will get set
because the state machine will be expecting
more data and the transmit machine will send the
inverted CRC after the byte which is presently
transmitting. Also, no message byte will be sent
on the next frame.
Caution should be taken when TRA gets set in
these cases because the TDUF error sequence
may engage before the user program has a
chance to rewrite the TXOP register with the cor-
rect opcode. If a TDUF error occurs, a subsequent
MSG write to the TXOP register will be used as the
first byte of the next frame.
010 Message Byte
MSG
011
Message Byte then
append CRC
MSG+CRC
100
In-Frame Response
Type 1
IFR1
101
In-Frame Response
Type 2
IFR2
110
In-Frame Response
Type 3
IFR3
111
IFR Type 3 then ap-
pend CRC
IFR3+CRC
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