ST7LITE49K2 Datasheet, PDF (45/245 Pages) STMicroelectronics – Communication interfaces

ST7LITE49K2
Supply, reset and clock management
7.3.2
Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated R_ON weak pull-up
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See Electrical Characteristic
section for more details.
A RESET signal originating from an external source must have a duration of at least
t_h(RSTL)in in order to be recognized (see Figure 16: Reset sequences). This detection is
asynchronous and therefore the MCU can enter reset state even in Halt mode.
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In
a noisy environment, it is recommended to follow the guidelines mentioned in the electrical
characteristics section.
Figure 15. Reset block diagram
V_DD
RESET
R_ON
Filter
PULSE
GENERATOR
INTERNAL
RESET
___ _{WATCHDOG RESET}
___ _{ILLEGAL OPCODE RESET} 1)
___ _{LVD RESET}
7.3.3
7.3.4
1. See Section 12.2.1: Illegal opcode reset on page 189 for more details on illegal opcode reset conditions.
External power-on reset
If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must
ensure by means of an external reset circuit that the reset signal is held low until V_DD is over
the minimum level specified for the selected f_OSC frequency.
A proper reset signal for a slow rising V_DD supply can generally be provided by an external
RC network connected to the RESET pin.
Internal low voltage detector (LVD) reset
Two different Reset sequences caused by the internal LVD circuitry can be distinguished:
● Power-on reset
● Voltage drop reset
The device RESET pin acts as an output that is pulled low when V_DD is lower than V_IT+
(rising edge) or V_DD lower than V_IT- (falling edge) as shown in Figure 16.
The LVD filters spikes on V_DD larger than t_g(VDD) to avoid parasitic resets.
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