ST7LITE49K2 Datasheet, PDF (43/245 Pages) STMicroelectronics – Communication interfaces

ST7LITE49K2
Supply, reset and clock management
Table 6. ST7 clock sources
Hardware configuration
ST7
OSC1
OSC2
EXTERNAL
SOURCE
ST7
OSC1
OSC2
C_L1
C_L2
LOAD
CAPACITORS
ST7
OSC1
OSC2
7.3
7.3.1
Note:
Reset sequence manager (RSM)
Introduction
The reset sequence manager includes three RESET sources as shown in Figure 15:
● External RESET source pulse
● Internal LVD RESET (Low Voltage Detection)
● Internal WATCHDOG RESET
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to Section 12.2.1 on page 189 for further details.
These sources act on the RESET pin and it is always kept low during the delay phase.
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
mapping.
The basic RESET sequence consists of 3 phases as shown in Figure 14:
● Active Phase depending on the RESET source
● 256 CPU clock cycle delay (see Table 7)
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