ST7LITE49K2 Datasheet, PDF (129/245 Pages) STMicroelectronics – Communication interfaces

ST7LITE49K2
On-chip peripherals
The OCiR register value required for a specific timing application can be calculated using
the following formula:
Equation 5
OCiR value =
t _* f_{CPU - 5}
PRESC
Where:
t=
signal or pulse period (in seconds)
f_CPU =
PRESC ⁼
CPU clock frequency (in hertz)
timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see : Timer A control
register 2 (TACR2) on page 132)
If the timer clock is an external clock the formula is:
Equation 6
OCiR = t _* f_EXT -5
Where:
t=
signal or pulse period (in seconds)
f_EXT = external timer clock frequency (in hertz)
The output compare 2 event causes the counter to be initialized to FFFCh (see Figure 67)
Note: 1 The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the output
compare interrupt is inhibited.
2 The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce
a timer interrupt if the ICIE bit is set and the I bit is cleared.
3 In PWM mode the ICAP1 pin can not be used to perform input capture because it is
disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be
set and IC2R can be loaded) but the user must take care that the counter is reset each
period and ICF1 can also generates interrupt if ICIE is set.
4 When the pulse width modulation (PWM) and one pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
11.4.4 Low power modes
Table 42. Effect of low power modes on 16-bit timer
Mode
Description
No effect on 16-bit timer.
Wait
Timer interrupts cause the device to exit from Wait mode.
16-bit timer registers are frozen.
In Halt mode, the counter stops counting until Halt mode is exited. Counting resumes from
the previous count when the device is woken up by an interrupt with ‘exit from Halt mode’
Halt ^{capability or from the counter reset value when the device is woken up by a reset.}
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is
armed. Consequently, when the device is woken up by an interrupt with ‘exit from Halt
mode’ capability, the ICFi bit is set, and the counter value present when exiting from Halt
mode is captured into the ICiR register.
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