ST92F124_06 Datasheet, PDF (414/429 Pages) STMicroelectronics – 8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E3 TM(EMULATED EEPROM), CAN 2.0B AND J1850 BLPD

ST92F124/F150/F250 - KNOWN LIMITATIONS
KNOWN LIMITATIONS (Cont’d)
13.6 CAN FIFO CORRUPTION WHEN 2 FIFO MESSAGES ARE PENDING
Description
Under certain conditions, FIFO corruption can
occur in the following cases:
WHEN a bxCAN RX FIFO already holds 2 mes-
sages (i.e. FMP==2)
WHILE the bxCAN requests the transfer of a new
receive message into the FIFO (this lasts one CPU
cycle)
THEN the internal FIFO pointer is not updated
BUT the FMP bits are updated correctly
AND the application releases the same FIFO
(with the instruction CANx_CTRL_CRFRy |=
CRF_rfom;
x=0 for the CAN_0 cell
x=1 for the CAN_1 cell
y=0 for the Receive FIFO 0
y=1 for the Receive FIFO 1 )
Figure 2. FIFO Corruption
Impact on Application:
As the FIFO pointer is not updated correctly, this
causes the last message received to be over-
written by any incoming message. This means one
message is lost as shown in the example in Figure
2 The bxCAN will not recover normal operation
until a device reset occurs.
Initial State
FMP
0
FIFO
*v
---
When the FIFO is empty, v and * point to the same location
Receive Message A 1
Receive Message B 2
Receive Message C 3
Release Message A 2
Release Message B
and Receive Message D
2
Receive Message E 3
Release Message C 2
Release Message E 1
Release Message B 0
v*
A- -
v*
AB-
v*
ABC
*v
ABC
*v
DBC
*v
DBC
*v
EBC
v*
EBC
v
*
EBC
*v
EBC
* does not move because FIFO is full (normal operation)
Normal operation
* Does not move, pointer curruption
D is overwritten by E
C released
E released instead of B
* and v are not pointing to the same message
the FIFO is empty
* pointer to next receive location
v pointer to next message to be released
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