ST92F124_06 Datasheet, PDF (123/429 Pages) STMicroelectronics – 8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E3 TM(EMULATED EEPROM), CAN 2.0B AND J1850 BLPD

ST92F124/F150/F250 - ON-CHIP DIRECT MEMORY ACCESS (DMA)
DMA TRANSACTIONS (Cont’d)
When selecting the DMA transaction with memory,
bit DCPR.RM (bit 0 of DCPR) must be cleared.
To select between using the ISR or the DMASR reg-
ister to extend the address, (see Memory Manage-
ment Unit chapter), the control bit DAPR.PS (bit 0
of DAPR) must be cleared or set respectively.
The DMA transaction Counter must be initialized
with the number of transactions to perform and will
be decremented after each transaction. The DMA
Address must be initialized with the starting ad-
dress of the DMA table and is increased after each
transaction. These two registers must be located
between addresses 00h and DFh of the Register
File.
Once a DMA channel is initialized, a transfer can
start. The direction of the transfer is automatically
defined by the type of peripheral and programming
mode.
Once the DMA table is completed (the transaction
counter reaches 0 value), an Interrupt request to
the CPU is generated.
When the Interrupt Pending (IDCR.IP) bit is set by
a hardware event (or by software), and the DMA
Mask bit (IDCR.DM) is set, a DMA request is gen-
erated. If the Priority Level of the DMA source is
higher than, or equal to, the Current Priority Level
(CPL), the DMA transfer is executed at the end of
the current instruction. DMA transfers read/write
data from/to the location pointed to by the DMA
Address Register, the DMA Address register is in-
cremented and the Transaction Counter Register
is decremented. When the contents of the Trans-
action Counter are decremented to zero, the DMA
Mask bit (DM) is cleared and an interrupt request
is generated, according to the Interrupt Mask bit
(End of Block interrupt). This End-of-Block inter-
rupt request is taken into account, depending on
the PRL value.
WARNING. DMA requests are not acknowledged
if the top level interrupt service is in progress.
Figure 58. DMA Between Memory and Peripheral
IDCR
IVR
DAPR
DCPR
DATA
PERIPHERAL
PAGED REGISTERS
DMA TRANSACTION
FFh
PAGED
REGISTERS
F0h
EFh
SYSTEM
REGISTERS
E0h
DFh
DATA
ALREADY
TRANSFERRED
DMA
TABLE
DMA
TRANSACTION
COUNTER
END OF BLOCK
INTERRUPT
SERVICE ROUTINE
DMA
ADDRESS
REGISTER FILE
000100h
000000h
ISR ADDRESS
MEMORY
VECTOR
TABLE
n
123/429
9