STCC02-ED5 Datasheet, PDF (4/13 Pages) STMicroelectronics – CONTROL CIRCUIT FOR HOME APPLIANCE MCU BASED APPLICATION

STCC02-ED5
The Zero Voltage Synchronization ZVS circuit generates a low frequency clock using the AC line cycles
(20 ms on 50 Hz or 16.7 ms on 60 Hz). This clock allows the MCU to generate the cooking timings and to
reduce the magnetron inrush current by powering it on at the AC line peak voltage.
RZV = 10 kΩ; VCC = 15 V; ICC = 20 mA
VZVS
50µs
115µs
FALLING EDGE
VTF
2V / div
40µs / div
RISING EDGE
The input pin SYN is an image of the mains voltage and is usually connected to the supply transformer
through a resistor R_ZV.
The circuit is protected against fast line transients because its state change will act on the whole MCU
routines: a 30 µs filter is implemented giving a higher immunity to the MCU circuit.
Since the ZVS pin connected to the Non Maskable Interrupt NMI or INT\ of the MCU, its falling edge is the
active counting event. The delay between the real Zero Crossing event and this ZVS falling edge depends
on the internal filtering time, the resistance R_ZV, the transformer, the rectifier drop voltage V_F, the V_CC sup-
ply load and the temperature. The STCC02 contribution to this delay can be evaluated by measuring the
delay between its input voltage V_TF and its output voltage V_ZVS. When using V_F = 0.8V, R_ZV = 10 kΩ, V_CC
= 15V, I_CC = 20 mA, it is about 50 µs on rising voltage V_TF and 115 µs on falling voltage V_TF.
■ Door closed detection circuit
VCC
DS
Door Switch
50 kΩ
VDD
VDD
EMI Filter
500 Ω
CDD
25 kΩ
The magnetron of the oven can be powered only if the door is closed in order to protect the oven user.
This safety feature is ensured mechanically by putting the door switch in series with the magnetron relay
coil supply.
For redundancy purpose, the Door Closed Detection CDD signal is also transmitted to the MCU. Since the
DS input detects the door state from an electromechanical switch, a spike suppressor is added to increase
its robustness. Its EMI immunity in off state (open door) is increased thanks to a 50kΩ pull down resistor
that maintains the DS signal in low state. When DS is high (24V), CDD signal is also in high state (5V).
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