STCC02-ED5 Datasheet, PDF (3/13 Pages) STMicroelectronics – CONTROL CIRCUIT FOR HOME APPLIANCE MCU BASED APPLICATION

STCC02-ED5
Its output voltage accuracy, that contributes to the ADC accuracy of the MCU, is better than ± 10 % in the
whole operating range of the temperature T_AMB, the load current I_DD and the input voltage V_IN. The
STCC02 input voltage range from 7 to 27 V; and its DC output current is less than 20 mA to keep the inter-
nal dissipation compatible with thermal package capability.
The regulator includes also an over current limiter to prevent high current conditions during the power up
inrush or the output short circuit. This limiter is made of a serial shunt resistance as current sensor and a
circuit that regulates the input over current.
■ The reset circuit
This circuit ensures a Low Voltage Detection (LVD) of the output voltage of the regulator. Most micro-
controllers have an active RESET pin in the low state: so, the /RST pin will be active at low state.
VH = 4.25 V
VL = 3.75 V
PROGRAMMABLE ^VDD
VH
DELAY
VL
NOISE FILTER
500 Ω
VDD
/RST
DLC
External
Capacitor
CUP
If CUP = 47 nF, TUP = 6 ms
V_DD
T_UP = 6 ms
C_UP = 47 nF
circuit output
RST\
internal latch output
T_DW ~ 40 µs
The reset circuit senses the regulator voltage V_DD. Its comparator with hysteresis achieves this task.
The /RST pin is high when V_DD is higher than the high threshold V_H = 4.25 V; and is low when the V_DD
decreases below the low threshold V_L = 3.75 V.
The comparator output changes are filtered for a high immunity. When the reset is disabling (V_DD > V_H),
the /RST signal rises after the delay time T_UP. This delay is set by an external capacitor C_UP connected
to the DL_C pin: T_UP = 6 ms for C_UP = 47 nF.
When the reset is enabling (V_DD < V_L), the /RST signal is falling after a delay time T_DW that is internally
set at 40 µs when C_UP = 47 nF.
■ The Zero Voltage Synchronization ZVS Circuit
AC
LINE
VCC
RZV
VTF
SYN
VDD
25 kΩ
100 kΩ
20 µs Filter
S1
Q
S2
ZVS
500 Ω
VZVS
COM
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