STW82101B Datasheet, PDF (34/68 Pages) STMicroelectronics – RF down converter with embedded integer-N synthesizer

I2C bus interface
9
I²C bus interface
STW82101B
The I²C bus interface is selected by hardware connection of the pin 25 (DBUS_SEL) to 0 V.
Data transmission from a microprocessor to the STW82101B takes place through the 2
wires (SDA and SCL) I²C-bus interface. The STW82101B is always a slave device.
The I²C-bus protocol defines any device that sends data on to the bus as a transmitter and
any device that reads the data as receiver. The device that controls the data transfer is
known as the master and the others as slaves. The master always initiates the transfer and
provides the serial clock for synchronization.
The STW82101B I²C bus supports Fast Mode operation (clock frequency up to 1 MHz).
9.1
9.1.1
I²C general features
Data validity
Data changes on the SDA line must only occur when the SCL is LOW. SDA transitions while
the clock is HIGH identify START or STOP conditions.
Figure 14. Data validity waveform
SDA
SCL
Data line stable Change
data valid
data allowed
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Doc ID 018503 Rev 3