STM32F765XX Datasheet, PDF (33/255 Pages) STMicroelectronics – Dual mode Quad-SPI

STM32F765xx STM32F767xx STM32F768Ax STM32F769xx
Functional overview
Figure 8. Regulator OFF
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The following conditions must be respected:
• V_DD should always be higher than V_{CAP_1} and V_{CAP_2} to avoid current injection
between power domains.
• If the time for V_{CAP_1} and V_{CAP_2} to reach V₁₂ minimum value is faster than the time for
V_DD to reach 1.7 V, then PA0 should be kept low to cover both conditions: until V_{CAP_1}
and V_{CAP_2} reach V₁₂ minimum value and until V_DD reaches 1.7 V (see Figure 9).
• Otherwise, if the time for V_{CAP_1} and V_{CAP_2} to reach V₁₂ minimum value is slower
than the time for V_DD to reach 1.7 V, then PA0 could be asserted low externally (see
Figure 10).
• If V_{CAP_1} and V_{CAP_2} go below V₁₂ minimum value and V_DD is higher than 1.7 V, then a
reset must be asserted on PA0 pin.
The minimum value of V₁₂ depends on the maximum frequency targeted in the application.
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