STM32F765XX Datasheet, PDF (26/255 Pages) STMicroelectronics – Dual mode Quad-SPI

Functional overview
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx
2.13
JPEG codec (JPEG)
The JPEG codec provides an fast and simple hardware compressor and decompressor of
JPEG images with full management of JPEG headers.
The JPEG codec main features:
• 8-bit/channel pixel depths
• Single clock per pixel encoding and decoding
• Support for JPEG header generation and parsing
• Up to four programmable quantization tables
• Fully programmable Huffman tables (two AC and two DC)
• Fully programmable minimum coded unit (MCU)
• Encode/decode support (non simultaneous)
• Single clock Huffman coding and decoding
• Two-channel interface: Pixel/Compress In, Pixel/Compressed Out
• Stallable design
• Support for single, greyscale component
• Functionality to enable/disable header processing
• Internal register interface
• Fully synchronous design
• Configured for high-speed decode mode
2.14
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 25 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 168 GPIOs can be connected
to the 16 external interrupt lines.
2.15
Clocks and startup
On reset the 16 MHz internal HSI RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy. The application can
then select as system clock either the RC oscillator or an external 4-26 MHz clock source.
This clock can be monitored for failure. If a failure is detected, the system automatically
switches back to the internal RC oscillator and a software interrupt is generated (if enabled).
This clock source is input to a PLL thus allowing to increase the frequency up to 216 MHz.
Similarly, full interrupt management of the PLL clock entry is available when necessary (for
example if an indirectly used external oscillator fails).
Several prescalers allow the configuration of the two AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB
buses is 216 MHz while the maximum frequency of the high-speed APB domains is
108 MHz. The maximum allowed frequency of the low-speed APB domain is 54 MHz.
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