ST10F167 Datasheet, PDF (33/69 Pages) STMicroelectronics – 16-BIT MCU WITH 128K BYTE FLASH MEMORY

ST10F167
Table 17.1 Instruction Set (cont’d)
Mnemonic
JBC
JNBS
CALLA, CALLI, CALLR
CALLS
PCALL
TRAP
PUSH, POP
SCXT
RET
RETS
RETP
RETI
SRST
IDLE
PWRDN
SRVWDT
DISWDT
EINIT
ATOMIC
EXTR
EXTP(R)
EXTS(R)
NOP
Description
Jump relative and clear bit if direct bit is set
Jump relative and set bit if direct bit is not set
Call absolute/indirect/relative subroutine if condition is met
Call absolute subroutine in any code segment
Push direct word register onto system stack and call
absolute subroutine
Call interrupt service routine via immediate trap number
Push/pop direct word register onto/from system stack
Push direct word register onto system stack and update
register with word operand
Return from intra-segment subroutine
Return from inter-segment subroutine
Return from intra-segment subroutine and pop direct
word register from system stack
Return from interrupt service subroutine
Software Reset
Enter Idle Mode
Enter Power Down Mode (assumes NMI-pin low)
Service Watchdog Timer
Disable Watchdog Timer
Signify End-of-Initialization on RSTOUT-pin
Begin ATOMIC sequence
Begin EXTended Register sequence
Begin EXTended Page (and Register) sequence
Begin EXTended Segment (and Register) sequence
Null operation
Bytes
4
4
4
4
4
2
2
4
2
2
2
2
4
4
4
4
4
4
2
2
2/4
2/4
2
18 BOOTSTRAP LOADER
To activate the Boot-strap loader, a hardware re-
set with RSTIN pin low and an external pull-up re-
sistor connected to the ALE pin, is applied. This
forces the chip into a special test mode. The pro-
gram execution starts from 1K bytes ROM,
mapped from 0 to 3FF hex which is not accessible
in normal execution mode.
This test ROM contains a one-time programmable
flash EPROM, loaded with a self-test program plus
the Boot-strap loader program. When the Boot-
strap loader mode is activated, an instruction fetch
is performed from the test ROM regardless of the
configuration selected with the EBC0, EBC1 and
BUSACT pins. The reset vector in the test ROM
branches to the self-test program, while the Non-
Maskable Interrupt vector (NMI) branches to the
Boot-strap loader routine.
The self-test routine execution time is approxi-
mately 10ms. It terminates with a software reset
instruction (SRST), where the chip is restarted ac-
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