ST10F167 Datasheet, PDF (13/69 Pages) STMicroelectronics – 16-BIT MCU WITH 128K BYTE FLASH MEMORY

ST10F167
4 MEMORY ORGANIZATION
The memory space of the ST10F167 is configured
in a Von-Neumann architecture. Code memory,
data memory, registers and I/O ports are organ-
ized within the same linear address space which
includes 16 MBytes. The entire memory space can
be accessed bytewise or wordwise. Particular por-
tions of the on-chip memory have additionally
been made directly bit addressable.
The ST10F167 provides 128KBytes of on-chip
flash memory.
2 KBytes of on-chip Internal RAM are provided as
a storage for user defined variables, for the system
stack, general purpose register banks and even
for code. A register bank can consist of up to 16
wordwide (R0 to R15) and/or bytewide (RL0, RH0,
…, RL7, RH7) so-called General Purpose Regis-
ters (GPRs).
1024 bytes (2 * 512 bytes) of the address space
are reserved for the Special Function Register ar-
eas (SFR space and ESFR space). SFRs are
wordwide registers which are used for controlling
and monitoring functions of the different on-chip
units. Unused SFR addresses are reserved for
other/future members of the ST10 family.
2 KBytes of on-chip Extension RAM (XRAM) are
provided to store user data, user stacks or code.
The XRAM is accessed like external memory and
cannot be used for the system stack or register
banks, and is not bit-addressable. The XRAM al-
lows 16-bit accesses with maximum speed.
In order to meet the needs of designs where more
memory is required than is provided on chip, up to
16 MBytes of external RAM and/or ROM can be
connected to the microcontroller.
5 EXTERNAL BUS CONTROLLER
All of the external memory accesses are per-
formed by a particular on-chip External Bus Con-
troller (EBC). It can be programmed either to Sin-
gle Chip Mode when no external memory is re-
quired, or to one of four different external memory
access modes, which are as follows:
• 16-/18-/20-/24-bit Addresses, 16-bit Data,
Demultiplexed
• 16-/18-/20-/24-bit Addresses, 16-bit Data,
Multiplexed
• 16-/18-/20-/24-bit Addresses, 8-bit Data,
Multiplexed
• 16-/18-/20-/24-bit Addresses, 8-bit Data,
Demultiplexed
In the demultiplexed bus modes, addresses are
output on PORT1 and data is input/output on
PORT0. In the multiplexed bus modes both ad-
dresses and data use PORT0 for input/output.
Important timing characteristics of the external bus
interface (Memory Cycle Time, Memory Tri-State
Time, Length of ALE and Read Write Delay) have
been made programmable. This gives the choice
of a wide range of different types of memories and
external peripherals. In addition, different address
ranges may be accessed with different bus char-
acteristics. Up to 5 external CS signals (4 windows
plus default) can be generated in order to save ex-
ternal glue logic. Access to very slow memories is
supported via a particular ‘Ready’ function. A
HOLD/HLDA protocol is available for bus arbitra-
tion.
For applications which require less than 16
MBytes of external memory space, this address
space can be restricted to 1 MByte, 256 KByte or
to 64 KByte. In this case Port 4 outputs four, two or
no address lines. If an address space of 16
MBytes is used, it outputs all 8 address lines.
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