M50FLW080A Datasheet, PDF (30/64 Pages) STMicroelectronics – 8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory

Command interface
M50FLW080A, M50FLW080B
Table 13. Commands
Bus operations⁽¹⁾
Command
1st
2nd
3rd
4th
5th
Addr Data Addr Data Addr Data Addr Data Addr Data
Read Memory Array^(2),(3),(4) 1+
Read Status Register^(5),(3) 1+
Read Electronic Signature⁽³⁾ 1+
Program / Multiple Byte
program (FWH)^(6),(7),(4)
2
Quadruple Byte Program
(A/A Mux)^(6),(8)
5
Chip Erase⁽⁶⁾
2
Block Erase⁽⁶⁾
2
Sector Erase⁽⁶⁾
2
Clear Status Register⁽⁹⁾
1
Program/Erase suspend⁽¹⁰⁾ 1
Program/Erase resume⁽¹¹⁾ 1
1
1
Invalid reserved⁽¹²⁾
1
1
1
X
FFh
Read
Addr
Read (Read (Read (Read (Read
Data Addr2) Data2) Addr3) Data3)
(Read (Read
Addr4) Data4)
X 70h
X
Status
Reg
(X)
(Status
Reg)
(X)
(Status
Reg)
(X)
(Status
Reg)
X
90h or Sig Signat (Sig
98h Addr ure Addr)
(Signat
ure)
(Sig (Signatu (Sig (Signat
Addr) re) Addr) ure)
X
40h or Prog
10h Addr
Prog
Data
X
30h
A1
Prog
Data1
A2
Prog
Data2
A3
Prog
Data3
A4
Prog
Data4
X 80h X 10h
X 20h BA D0h
X 32h SA D0h
X 50h
X B0h
X D0h
X 00h
X 01h
X 60h
X 2Fh
X C0h
1. For all commands: the first cycle is a Write. For the first three commands (Read Memory, Read Status Register, Read
Electronic Signature), the second and next cycles are READ. For the remaining commands, the second and next cycles
are WRITE.
BA = Any address in the Block, SA = Any address in the Sector. X = Don’t Care, except that A22=1 (for FWH or LPC
mode), and A21 and A20 are set according to the rules shown in Table 5 (for LPC mode)
2. After a Read Memory Array command, read the memory as normal until another command is issued.
3. “1+” indicates that there is one write cycle, followed by any number of read cycles.
4. Configuration registers are accessed directly without using any specific command code. A single Bus Write or Bus Read
Operation is all that is needed.
5. After a Read Status Register command, read the Status Register as normal until another command is issued.
6. After the erase and program commands read the Status Register until the command completes and another command is
issued.
7. Multiple Byte Program PA= start address, A0 (Double Byte Program) A0 and A1 (Quadruple Byte Program) are Don`t
Care. PD is two or four Bytes depending on Msize code.
8. Addresses A1, A2, A3 and A4 must be consecutive addresses, differing only in address bits A0 and A1.
9. After the Clear Status Register command bits SR1, SR3, SR4 and SR5 in the Status Register are reset to ‘0’.
10. While an operation is being Program/Erase Suspended, the Read Memory Array, Read Status Register, Program (during
Erase Suspend) and Program/Erase Resume commands can be issued.
11. The Program/Erase Resume command causes the Program/Erase suspended operation to resume. Read the Status
Register until the Program/Erase Controller completes and the memory returns to Read Mode.
12. Do not use Invalid or Reserved commands.
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