M50FLW080A Datasheet, PDF (23/64 Pages) STMicroelectronics – 8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory

M50FLW080A, M50FLW080B
Bus operations
Table 9. LPC Bus Write field definitions (1 byte)
Clock Clock
Cycle Cycle
Number Count
Field
LAD0- Memory
LAD3
I/O
Description
On the rising edge of CLK with LFRAME Low,
1
1
START 0000b
I the contents of LAD0-LAD3 must be 0000b to
indicate the start of a LPC cycle.
2
1
CYCTYPE
+ DIR
011Xb
Indicates the type of cycle. Bits 3:2 must be
I 01b. Bit 1 indicates the direction of transfer: 1b
for write. Bit 0 is don’t care (X).
3-10
8
ADDR XXXX
11-12 2
DATA
XXXX
A 32-bit address is transferred, with the most
significant nibble first. A23-A31 must be set to
I 1. A22=1 for memory access, and A22=0 for
register access. Table 5 shows the appropriate
values for A21-A20.
I
Data transfer is two cycles, starting with the
least significant nibble.
13
1
TAR
1111b
I
The host drives LAD0-LAD3 to 1111b to
indicate a turnaround cycle.
14
1
TAR
1111b
(float)
O
The LPC Flash Memory takes control of LAD0-
LAD3 during this cycle.
The LPC Flash Memory drives LAD0-LAD3 to
15
1
SYNC 0000b
O 0000b, indicating it has received data or a
command.
16
1
TAR
1111b
O
The LPC Flash Memory drives LAD0-LAD3 to
1111b, indicating a turnaround cycle.
17
1
TAR
1111b
(float)
N/A
The LPC Flash Memory floats its outputs and
the host takes control of LAD0-LAD3.
Figure 9. LPC Bus Write waveforms (1 byte)
CLK
LFRAME
LAD0-LAD3
Number of
clock cycles
START
1
CYCTYPE
+ DIR
1
ADDR
8
DATA
2
TAR
2
SYNC
1
TAR
2
AI04430
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