STE36N50-DK Datasheet, PDF (3/9 Pages) STMicroelectronics – N-CHANNEL ENHANCEMENT MODE POWERMOS TRANSISTORANDULTRA-FAST DIODEINISOTOPPACKAGE

STE36N50-DK
MOSFET ELECTRICAL CHARACTERISTICS (continued)
DYNAMIC
Symb ol
g_fs (∗)
Ciss
Coss
Crss
Parameter
Forward
Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
Test Conditions
V_DS > I_{D (on)} x R_DS(on)max I_D = 18 A
VDS = 25 V f = 1 MHz VGS = 0
Min.
16
Typ.
Max.
8000
1300
350
Unit
S
pF
pF
pF
SWITCHING ON
Symb ol
td(on)
tr
(di/ d t) _{o n}
Qg
Q_gs
Q_gd
Parameter
Turn-on Time
Rise Time
Turn-on Current Slope
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Test Conditions
VDD = 250 V ID = 18 A
RG = 4.7 Ω
VGS = 10 V
(see test circuit, figure 1)
V_DD = 400 V I_D = 36 A
RG = 4.7 Ω
VGS = 10 V
(see test circuit, figure 3)
VDD = 400 V ID = 36 A VG S = 10 V
Min.
Typ.
45
85
700
295
35
145
Max.
65
120
Unit
ns
ns
A/µs
nC
nC
nC
SWITCHING OFF
Symb ol
t_{r(Vof f)}
t_f
tc
Parameter
Off-voltage Rise Time
Fall Time
Cross-over Time
Test Conditions
V_DD = 400 V I_D = 36 A
R_G = 4.7 Ω V_GS = 10 V
(see test circuit, figure 3)
Min.
Typ.
100
45
160
Max.
140
65
225
Unit
ns
ns
ns
SOURCE DRAIN DIODE
Symb ol
Parameter
Test Conditions
IS D
I SDM(•)
Source-drain Current
Source-drain Current
(pulsed)
V_SD (∗) Forward On Voltage
I_SD = 36 A V_GS = 0
trr
Reverse Recovery
Time
ISD = 36 A di/dt = 100 A/µs
V_DD = 100 V T_j = 150 ^oC
Q_rr Reverse Recovery
Charge
(see test circuit, figure 3)
IRRM Reverse Recovery
Current
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(•) Pulse width limited by safe operating area
Min.
Typ.
Max.
36
144
Unit
A
A
1.4
V
1
µs
29
µC
58
A
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