STD9N10 Datasheet, PDF (3/10 Pages) STMicroelectronics – N - CHANNEL ENHANCEMENT MODE POWER MOS TRANSISTOR

STD9N10
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symb ol
t_d(on)
tr
(di/ dt) on
Q_g
Q_gs
Q_gd
P a ram et er
Turn-on T ime
Rise Time
Turn-on Current Slope
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Test Conditions
V_DD = 50 V I_D = 4.5 A
RG = 4.7 Ω
VGS = 10 V
(see test circuit, figure 3)
VDD = 80 V
ID = 9 A
R_G = 4.7 Ω
V_GS = 10 V
(see test circuit, figure 5)
V_DD = 80 V I_D = 9 A V_GS = 10 V
Min.
Typ .
10
40
M a x.
15
60
Unit
ns
ns
440
A/µs
15
25
nC
6
nC
5
nC
SWITCHING OFF
Symb ol
t_{r(Vo f f)}
tf
t_c
P a ram et er
Off-voltage Rise Time
Fall Time
Cross-over T ime
Test Conditions
V_DD = 80 V I_D = 9 A
RG = 4.7 Ω VGS = 10 V
(see test circuit, figure 5)
Min.
Typ .
15
25
50
M a x.
25
35
70
Unit
ns
ns
ns
SOURCE DRAIN DIODE
Symb ol
P a ram et er
Test Conditions
I_SD
ISDM (•)
Source-drain Current
Source-drain Current
( pu ls ed)
VSD (∗) Forward O n Volt age
ISD = 9 A VGS = 0
t_rr
Reverse Recovery
Time
Q_rr
Reverse Recovery
Charge
I_SD = 9 A
di/dt = 100 A/µs
VDD = 20 V Tj = 150 ^oC
(see test circuit, figure 5)
I_RRM
Reverse Recovery
Cu r re nt
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(•) Pulse width limited by safe operating area
Min.
Typ .
M a x.
9
36
Unit
A
A
1.5
V
80
ns
0.2
µC
5
A
Safe Operating Area
Thermal Impedance
3/10