ESDAVLC8-1BU2 Datasheet, PDF (3/11 Pages) STMicroelectronics – Single-line low capacitance Transil

ESDAVLC8-1BU2
Characteristics
Figure 3.
Relative variation of peak pulse
power versus initial junction
temperature
P_PP[T_j initial] / P_PP [T_j initial=25°C]
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
T_j(°C)
0.0
0
25
50
75
100
125
150
Figure 4. Peak pulse power versus
exponential pulse duration
P_PP(W)
1000
T_j initial = 25°C
100
10
1
tP(µs)
10
100
1000
Figure 5.
Junction capacitance versus
reverse applied voltage
(typical values)
C(pF)
5
4
F=1MHz
V_OSC=30mV_RMS
T_j=25°C
3
2
1
VR (V)
0
Figure 6.
Relative variation of leakage
current versus junction
temperature (typical values)
I_R [T_j] / I_R [T_j=25°C]
100
V_R =3V
10
Tj(°C)
1
25
50
75
100
125
Figure 7. ESD response to IEC 61000-4-2
(+8 kV contact discharge)
Figure 8. ESD response to IEC 61000-4-2
(-8 kV contact discharge)
10 V/Div
10 V/Div
20 ns/Div
20 ns/Div
Doc ID 16546 Rev 2
3/11