ESDAVLC8-1BM2 Datasheet, PDF (3/13 Pages) STMicroelectronics – Single line low capacitance Transil for ESD protection

ESDAVLC8-1BM2, ESDAVLC8-1BT2
Characteristics
Figure 3.
Relative variation of peak pulse
power versus initial junction
temperature
Figure 4.
Junction capacitance versus
reverse voltage applied
(typical values, direct and reverse)
1.1 ^{PPP[Tjinitial] /PPP[Tjinitial = 25 °C]}
1.0
0.9
0.8
C(pF)
5
4
F = 1 MHz
V_OSC= 30 mV_RMS
T_j = 25 °C
0.7
3
0.6
0.5
2
0.4
0.3
0.2
1
0.1
0.0
T_j (°C)
0
V_LINE (V)
0
25
50
75
100
125
150
0
1
2
3
4
5
6
Figure 5.
Peak pulse power versus
Figure 6.
exponential pulse duration (direct)
Peak pulse power versus
exponential pulse duration
(reverse)
10000 ^{PPP (W)}
10000 ^{PPP (W)}
1000
1000
100
100
10
10
1
t_P (µs)
1
t_P (µs)
1
10
100
1000
1
10
100
1000
Figure 7.
I_PP (A)
10.0
Clamping voltage versus peak
pulse current (typical values,
exponential waveform, direct)
Figure 8.
10.0 ^{IPP (A)}
Clamping voltage versus peak
pulse current (typical values,
exponential waveform, reverse)
1.0
0.1
16
1.0
V_CL (V)
0.1
V_CL (V)
18
20
10
12
14
16
Doc ID 16937 Rev 1
3/13