STV0974 Datasheet, PDF (27/69 Pages) STMicroelectronics – Mobile Imaging DSP

Functional description
STV0974
4 DRQ is released after the first byte is read.
5 After the last byte of the burst is read, the transfer terminates on step 6 if the FIFO is empty and
the frame end is reached. Otherwise, transfer continues on step 2.
6 IRQ is asserted to signal the end of image transfer; the DMA channel is closed and re-initialized
for the next transfer.
This behavior ensures that no request can be missed by the controller, assuming DRQ is an edge-
sensitive signal. DRQ polarity can be reversed through MICR[POL] bit.
Note: 1 During DMA transfer, it is assumed that reading DR returns a byte from the FIFO, which means that
AR shall be pointing to the FIFO when the DMA channel is active. To access other registers while
performing DMA, the DMA controller must be halted and pending transfers properly flushed; then
indirect accesses to the camera subsystem can occur. Finally, AR must be restored and the DMA
controller released.
2 At the end of the transfer, FIFO underrun can occur if the image size is not an integer multiple of the
burst size: dummy bytes are appended at the end of the image buffer. Nevertheless, the JPEG end-
of-frame marker (0xffd9) delineates the buffer.
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