STV0974 Datasheet, PDF (25/69 Pages) STMicroelectronics – Mobile Imaging DSP

Functional description
STV0974
Interrupt Mask Register (IMASK)
Table 16: Interrupt Mask Register
Bits Name Type
Description
[7:6]
-
-
[5:0]
IMASK RW
Reserved
Each IMASK bit set to ‘1’ enables the corresponding interrupt source bit in the status
register (SR)
Interrupt Clear Register (ICLR)
Table 17: Interrupt Clear Register
Bits Name Type
Description
[7:6]
[5:2]
[1:0]
-
ICLR
-
-
Reserved
WO Each ICLR bit written with a ‘1’ clears the corresponding interrupt source bit in the
status register (SR). Writing a ‘0’ has no effect
-
Reserved
FIFO Threshold Register (FTHR)
Table 18: FIFO threshold register
Description
FTRH
NE = 1
NE = 0
Holds the FIFO threshold value
threshold = 1
threshold = TH * 16
(TH is ignored)
(TH valid range is [1, 2...127])
This register is used to program values such as 1 (flush), 16 or 32 (DMA burst) or any greater value
up to 2032 for interrupt driven data transfer. Note that for proper DMA operation, ‘threshold’ must be
greater than or equal to the DMA burst size (MICR[BSIZE]).
Table 19: FIFO Threshold Register
Bits Name Type
Description
[15:11] -
[10:4] TH
[3:1]
-
0
NE
-
Reserved
RW
Threshold value in 16-byte increments.
-
Reserved
RW
Not Empty:
1 = Force threshold to 1 (TH is ignored)
0 = Normal
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