TDA7437N_06 Datasheet, PDF (26/34 Pages) STMicroelectronics – Digitally controlled audio processor

Mute and pause features
TDA7437N
5.9
I²C bus read mode
The TDA7437N sends the master a 1 byte "transmitted info" via I²C bus in read mode.
The read mode is master activated by sending the chip address with LSB set to 1, followed
by an acknowledge bit.
The TDA7437N recognizes the request. At the following master generated clock bits, the
TDA7437N issues the transmitted inFO byte on the SDA data bus line (MSB transmitted
first).
At the ninth clock bit the MCU master can:
● acknowledge the reception, starting in this way the transmission of another byte from
the TDA7437N.
● no acknowledge, stopping the read mode communication.
5.10
Loudness stage
The previous SGS-THOMSON audioprocessors implemented a fixed loudness response,
only ON/OFF sw programmable.
No possibility to change the loud boost rate at a certain volume level. The TDA7437N
implements a fully programmable loudness control in 20 steps of 1dB.
It allows a customized loudness response for each application. The external network
connected to the loudness pins LOUD_L and LOUD_R fixes the type of loudness response.
1. Simple capacitor. The loudness effect is only a boost of low frequencies.
(see Figure 19)
2. Second order loudness (boost of low and high frequencies).
3. Second order decreased type loudness (lower boost of low and high frequencies).
4. Second order modified type loudness (higher boost of low and high frequencies).
5.11
Treble stage
The treble stage is a simple high pass filter, it’s time constant is fixed by internal resistor
(typically 50Kohm), and an external capacitor, connected between pins TREB_R/TREB_L
and ground.
5.12
IN-OUT pins
The multiplexer output is available at OUT_R and OUT_L pins for the optional connection of
an external graphic equalizer (TDA7316/TDA7317), surround chip (TDA7346) etc. The
signal is fed in again at pins IN_L and IN-R. In the case of an application without any
external devices, the pins OUT_L/OUT_R and IN_L/IN_R can be left unconnected, if bit D3
byte input selector is forced = 0 (DC connect). Instead if bit D3 is kept = 1 an external
decoupling capacitor must be provided between OUTR/INR and OUTL/INR to avoid signal
DC jumps, generating "clicking" output noise. The input impedance of the next volume stage
is 44Kohm typical (minimum 31Kohm). A capacitor no lower than 1mF should be used.
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