SPC564A70B4 Datasheet, PDF (26/133 Pages) STMicroelectronics – Up to 4 multiply and accumulate operations per cycle

Introduction
SPC564A70B4, SPC564A70L7
1.5.15
– Prefill mode to precondition the filter before the sample window opens
– Supports Multiple Cascading Decimation Filters to implement more complex filter
designs
– Optional Absolute Integrators on the output of Decimation Filters
● Full duplex synchronous serial interface (SSI) to an external device
– Free-running clock for use by an external device
– Supports a 26-bit message length
● Priority based queues
– Supports 6 queues with fixed priority. When commands of distinct queues are
bound for the same ADC, the higher priority queue is always served first
– Queue_0 can bypass all prioritization, buffering and abort current conversions to
start a Queue_0 conversion a deterministic time after the queue trigger
– Supports software and hardware trigger modes to arm a particular queue
– Generates interrupt when command coherency is not achieved
● External hardware triggers
– Supports rising edge, falling edge, high level and low level triggers
– Supports configurable digital filter
Deserial serial peripheral interface (DSPI)
The DSPI block provides a synchronous serial interface for communication between the
SPC564A70 MCU and external devices. The DSPI supports pin count reduction through
serialization and deserialization of eTPU and eMIOS channels and memory-mapped
registers. The channels and register content are transmitted using a SPI-like protocol. This
SPI-like protocol is completely configurable for baud rate, polarity and phase, frame length,
chip select assertion, etc. Each bit in the frame may be configured to serialize either eTPU
channels, eMIOS channels or GPIO signals. The DSPI can be configured to serialize data to
an external device that implements the Microsecond Bus protocol. There are three identical
DSPI blocks on the SPC564A70 MCU. The DSPI pins support 5 V logic levels or Low
Voltage Differential Signalling (LVDS) to improve high speed operation.
DSPI module features include:
● Selectable LVDS pads working at 40 MHz for SOUT and SCK pins for DSPI_B and
DSPI_C
● Support for downstream Micro Second Channel (MSC) with Timed Serial Bus (TSB)
configuration on DSPI_B and DSPI_C
● 3 sources of serialized data: eTPU_A, eMIOS output channels, and memory-mapped
register in the DSPI
● 4 destinations for deserialized data: eTPU_A and eMIOS input channels, SIU external
Interrupt input request, memory-mapped register in the DSPI
● 32-bit DSI and TSB modes require 32 PCR registers, 32 GPO and GPI registers in the
SIU to select either GPIO, eTPU or eMIOS bits for serialization
● The DSPI module can generate and check parity in a serial frame
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Doc ID 18078 Rev 4