M28F420 Datasheet, PDF (25/38 Pages) STMicroelectronics – 4 Megabit (x8 or x16, Block Erase) FLASH MEMORY

M28F410, M28F420
Table 21. Word/Byte Program, Erase Times
(TA = 0 to 70°C; VCC = 5V ± 10% or 5V ± 5%)
Parameter
Test Conditions
Main Block Program (Byte)
Main Block Program (Word)
Boot or Parameter Block Erase
Main Block Erase
VPP = 12V ±5%
V_PP = 12V ±5%
VPP = 12V ±5%
V_PP = 12V ±5%
M28F410 / 420
Min
Typ
Max
1.2
4.2
0.6
2.1
1
7
2.4
14
Unit
sec
sec
sec
sec
Table 22. Word/Byte Program, Erase Times
(TA = –40 to 85°C or –40 to 125°C; VCC = 5V ± 10% or 5V ± 5%)
Parameter
Main Block Program (Byte)
Main Block Program (Word)
Boot or Parameter Block Erase
Main Block Erase
Test Conditions
V_PP = 12V ±5%
VPP = 12V ±5%
VPP = 12V ±5%
VPP = 12V ±5%
M28F410 / 420
Min
Typ
Max
1.4
5
0.7
2.5
1.5
10.5
3
18
Unit
sec
sec
sec
sec
DEVICE OPERATION (cont’d)
E Chip Enable. The Chip Enable activates the
memory control logic, input buffers, decoders and
sense amplifiers. E High de-selects the memory
and reduces the power consumption to the standby
level. E can also be used to control writing to the
command register and to the memory array, while
W remains at a low level. Both addresses and data
inputs are then latched on the rising edge of E.
RP Reset/Power Down. This is a tri-level input
which locks the Boot Block from programming and
erasure, and allows the memory to be put in deep
power down.
When RP is High (up to 6.5V maximum) the Boot
Block is locked and cannot be programmed or
erased. When RP is above 11.4V the Boot Block is
unlockedfor programming or erasure. With RP Low
the memory is in deep power down, and if RP is
within V_SS+0.2V the lowest supply current is ab-
sorbed.
G Output Enable. The Output Enable gates the
outputs through the data buffers during a read
operation.
W Write Enable. It controls writing to the Com-
mand Register and Input Address and Data
latches. Both Addresses and Data Inputs are
latched on the rising edge of W.
BYTE Byte/Word Organization Select. This input
selects either byte-wide or word-wide organization
of the memory. When BYTE is Low the memory is
organized x8 or byte-wide and data input/output
uses DQ0-DQ7 while A-1 acts as the additional,
LSB, of the memory address that multiplexes the
upper or lower byte. In the byte-wide organization
DQ8-DQ14 are high impedance. When BYTE is
High the memory is organized x16 and data in-
put/output uses DQ0-DQ15 with the memory ad-
dressed by A0-A17.
VPP Program Supply Voltage. This supply voltage
is used for memory Programming and Erase.
V_PP ±10% tolerance option is provided for applica-
tion requiring maximum 100 write and erase cycles.
V_CC Supply Voltage. It is the main circuit supply.
V_SS Ground. It is the reference for all voltage
measurements.
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