M24M01-R_09 Datasheet, PDF (25/37 Pages) STMicroelectronics – 1 Mbit serial I²C bus EEPROM

M24M01-R, M24M01-W, M24M01-HR
DC and AC parameters
Table 14. AC characteristics at 1 MHz (M24M01-HR)
Test conditions specified in Table 7
Symbol Alt.
Parameter
Min.
Max.
Unit
f_C
f_SCL
Clock frequency
0
1
MHz
t_CHCL
t_HIGH Clock pulse width high
300
-
ns
t_CLCH
t_XH1XH2(1)
t_XL1XL2(1)
t_QL1QL2(2)(3)
t_LOW
t_R
t_F
t_F
Clock pulse width low
Input signal rise time
Input signal fall time
SDA (out) fall time
400
-
ns
-
120
ns
-
120
ns
-
120
ns
t_DXCH
t_SU:DAT Data in setup time
80
-
ns
t_CLDX
t_HD:DAT Data in hold time
0
-
ns
t_CLQX
t_DH Data out hold time
50
-
ns
t_CLQV(4)(5)
t_AA Clock low to next data valid (access time) 50
500
ns
t_CHDL(6)
t_SU:STA Start condition setup time
250
-
ns
t_DLCL
t_HD:STA Start condition hold time
250
-
ns
t_CHDH
t_SU:STO Stop condition setup time
250
-
ns
t_DHDL
t_BUF
Time between Stop condition and next
Start condition
500
-
ns
t_W
t_NS(2)
t_WR
Write time
-
Pulse width ignored (input filter on SCL
and SDA)
-
5
ms
50
ns
1. Input rise/fall time values recommended by the Fast-mode Plus I²C-bus specification. The M24xxx devices
accept longer input rise/fall times provided that these rise/fall times are compatible with all other timing
conditions defined in this AC table.
2. Characterized only, not tested in production.
3. The SDA(out) rise time is not defined by the M24xxx, it is defined by the application pull-up resistor
(connected on the SDA line) and, therefore, it is not specified in this table.
4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
5. t_CLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8V_CC, assuming
that the R_bus × C_bus time constant is within the range defined in Figure 6.
6. For a reStart condition, or following a Write cycle.
Doc ID 12943 Rev 7
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