M24M01-R_09 Datasheet, PDF (16/37 Pages) STMicroelectronics – 1 Mbit serial I²C bus EEPROM

Device operation
M24M01-R, M24M01-W, M24M01-HR
Figure 9. Write mode sequences with WC = 0 (data write enabled)
WC
Byte Write
ACK
ACK
ACK
ACK
Dev sel
Byte addr
Byte addr
Data in
R/W
WC
Page Write
ACK
ACK
ACK
ACK
Dev sel
Byte addr
Byte addr
Data in 1
Data in 2
R/W
WC (cont'd)
Page Write (cont'd)
ACK
ACK
Data in N
AI01106d
3.9
ECC (error correction code) and Write cycling
The M24M01-R, M24M01-HR and M24M01-W devices offer an ECC (error correction code)
logic which compares each 4-byte word with its six associated EEPROM ECC bits. As a
result, if a single bit out of 4 bytes of data happens to be erroneous during a Read operation,
the ECC detects it and replaces it by the correct value. The read reliability is therefore much
improved by the use of this feature.
Note however that even if a single byte has to be written, 4 bytes are internally modified
(plus the ECC word), that is, the addressed byte is cycled together with the three other bytes
making up the word. It is therefore recommended to write by packets of 4 bytes in order to
benefit from the larger amount of Write cycles.
The M24M01-R, M24M01-HR and M24M01-W devices are qualified at 1 million (1 000 000)
Write cycles, using a cycling routine that writes to the device by multiples of 4-byte words.
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Doc ID 12943 Rev 7