PSD8XXFX Datasheet, PDF (24/128 Pages) STMicroelectronics – Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 5 V

PSD register description and address offset
PSD8XXFX
5
PSD register description and address offset
Table 7 shows the offset addresses to the PSD registers relative to the CSIOP base
address. The CSIOP space is the 256 bytes of address that is allocated by the user to the
internal PSD registers. Table 8 provides brief descriptions of the registers in CSIOP space.
The following section gives a more detailed description.
Table 7. I/O port latched address output assignments⁽¹⁾⁽²⁾
MCU
Port A
Port A (3:0)
Port A (7:4)
Port B
Port B (3:0)
Port B (7:4)
8051XA (8-bit)
N/A
Address a7-a4 Address a11-a8 N/A
80C251 (page mode)
N/A
N/A
Address a11-a8
Address a15-
a12
All other 8-bit multiplexed Address a3-a0 Address a7-a4 Address a3-a0 Address a7-a4
8-bit non-multiplexed bus N/A
N/A
Address a3-a0 Address a7-a4
1. See Section 16: I/O ports, on how to enable the Latched Address Output function.
2. N/A = Not Applicable
Table 8. Register address offset
Register
name
Port A
Port B
Port C
Port D
Other
(1)
Description
Data In
00
01
10
11
Reads port pin as input, MCU I/O input
mode
Control
02
03
Selects mode between MCU I/O or
Address Out
Data Out
04
05
12
13
Stores data for output to port pins, MCU
I/O output mode
Direction
06
07
14
15
Configures port pin as input or output
Drive Select 08
09
16
17
Configures port pins as either CMOS or
Open Drain on some pins, while selecting
high slew rate on other pins.
Input
macrocell
0A 0B 18
Reads input macrocells
Enable Out 0C 0D 1A 1B
Reads the status of the output enable to
the I/O port driver
Output
macrocells 20
20
AB
READ – reads output of macrocells AB
WRITE – loads macrocell flip-flops
Output
macrocells
BC
21 21
READ – reads output of macrocells BC
WRITE – loads macrocell flip-flops
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Doc ID 7833 Rev 7