PSD8XXFX Datasheet, PDF (100/128 Pages) STMicroelectronics – Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 5 V

AC/DC parameters
PSD8XXFX
Figure 39. Input to output disable / enable
INPUT
tER
tEA
INPUT TO
OUTPUT
ENABLE/DISABLE
AI02863
Table 48. CPLD combinatorial timing (5 V devices)
Symbol
Parameter
-70
-90
-15
Conditions
Min Max Min Max Min Max
Fast
PT
Aloc
Turbo
off
Slew
rate
(1)
Unit
CPLD input
t_PD
pin/feedback to
CPLD combinatorial
output
20
25
32 + 2 + 10 – 2 ns
t_EA
CPLD input to CPLD
output enable
21
26
32
+ 10 – 2 ns
t_ER
CPLD input to CPLD
output disable
21
26
32
+ 10 – 2 ns
t_ARP
CPLD register clear
or preset delay
21
26
33
+ 10 – 2 ns
t_ARPW
CPLD register clear
or preset pulse width
10
20
29
+ 10
ns
t_ARD
CPLD array delay
Any
macrocell
11
16
22 + 2
ns
1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
Table 49. CPLD combinatorial timing (3 V devices)
Symbol
Parameter
Conditions
-12
Min Max
-15
Min Max
-20
Min Max
PT
Aloc
Turbo
off
Slew
rate
(1)
Unit
CPLD input
t_PD
pin/feedback to
CPLD combinatorial
output
t_EA
CPLD input to CPLD
output enable
t_ER
CPLD input to CPLD
output disable
t_ARP
CPLD register clear
or preset delay
40
45
50 + 4 + 20 – 6 ns
43
45
50
43
45
50
40
43
48
+ 20 – 6 ns
+ 20 – 6 ns
+ 20 – 6 ns
100/128
Doc ID 7833 Rev 7