PSD8XXFX Datasheet, PDF (104/128 Pages) STMicroelectronics – Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 5 V

AC/DC parameters
PSD8XXFX
Table 52. CPLD macrocell asynchronous clock mode timing (5 V devices) (continued)
Symbol Parameter
Conditions
-70
-90
Min Max Min Max
-15
Min Max
PT ^{Turbo Slew}
Aloc _{off rate}
Unit
t_COA
Clock to
output delay
21
30
t_ARDA
CPLD array
delay
Any macrocell
11
16
37
+ 10 – 2 ns
22 + 2
ns
t_MINA
Minimum
clock period
1/f_CNTA
16
28
39
ns
Table 53. CPLD macrocell Asynchronous clock mode timing (3 V devices)
Symbol Parameter
Conditions
-12
Min Max
-15
Min Max
-20
Min Max
PT ^Turbo Slew
Aloc _off rate
Unit
f_MAXA
t_SA
t_HA
t_CHA
t_CLA
t_COA
t_ARD
t_MINA
Maximum
frequency
External
feedback
1/(t_SA+t_COA)
21.7
19.2
16.9
MHz
Maximum
frequency
Internal
feedback
(f_CNTA)
1/(t_SA+t_COA–10)
27.8
23.8
20.4
Maximum
frequency
1/(t_CHA+t_CLA)
33.3
27
24.4
Pipelined data
MHz
MHz
Input setup time
10
12
13
+ 4 + 20
ns
Input hold time
12
15
17
ns
Clock high time
17
22
25
+ 20
ns
Clock low time
13
15
16
+ 20
ns
Clock to output
delay
36
40
46
+ 20 – 6 ns
CPLD array
delay
Any macrocell
25
29
33 + 4
ns
Minimum clock
period
1/f_CNTA
36
42
49
ns
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Doc ID 7833 Rev 7