M7040N Datasheet, PDF (22/159 Pages) STMicroelectronics – 64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE

M7040N
Figure 12. Clocks for All Timing Diagrams
CLK2X
P HS_L
(Use for CLK1X MODE)
CLK1X
(Use for CLK1X MODE)
AI04666
PLL USAGE
When the device first powers up, it takes 0.5 ms to
lock the internal phase-lock loop (PLL). During this
locking of the PLL, in addition to 32 extra CLK1X
cycles in CLK1X mode and 64 extra cycles in
CLK2X mode, the RST_L must be held low for
proper initialization of the device. Setup and hold
requirements will change in CLK1X mode if the
duty cycle of the CLK1X is varied. All signals into
the device in CLK1X mode are sampled by a clock
that is generated by multiplying CLK1X by two.
Since PLL has a locking range, the device will only
work between the range of frequencies specified
in the timing specification section.
REGISTERS
All registers in the M7040N are 72 bits wide. The
M7040N contains 16 pairs of comparand storage
registers, 16 pairs of global mask registers
(GMRs), eight search successful index registers
and one each of command, information, burst
READ, burst WRITE, and next-free address regis-
ters. Table 9 provides an overview of all the
M7040N registers. The registers are ordered in as-
cending address order. Each register group is then
described in the following subsections.
Table 9. Register Overview
Address Abbreviation
0–31
COMP0–31
32–47, 96–111
48–55
56
57
58
59
60
61–63
MASKS
SSR0–7
COMMAND
INFO
RBURREG
WBURREG
NFA
–
Type
R
RW
R
RW
R
RW
RW
R
–
Name
32 Comparand Registers. Stores comparands from the DQ Bus for
learning later.
16 Global Mask Registers Pairs.
8 SEARCH Successful Index Registers.
Command Register.
Information Register.
Burst Read Register.
Burst Write Register.
Next Free Address Register.
Reserved
22/159