AIS1120SX Datasheet, PDF (22/58 Pages) STMicroelectronics – Embedded self-test

Customer accessible data arrays (registers)
AIS1120SX / AIS2120SX
2.4
REG_STATUS
Table 6. REG_STATUS_0
REG_STATUS_0 (address: 0x03)
Name
Bit#
R/W
STATUS [1:0]
[7:6]
R
TESTMODE_ENABLED
5
R
REG_CTRL_0_WR_ERR⁽¹⁾
4
R
Not used
3
R
LOSS_CAP
2
R
END_OF_PWRUP
1
R
RST_ACTIVE
0
R
1. Bit not latched (cleared by any read command).
Reset
state
00
0
0
0
0
0
0
Description
Status Error bits:
if = "00" device is in initialization phase (power-up,
configuration, fast offset cancellation);
if = "01" device is in normal mode (EOI = 1);
if = "10" device is test phase (0 g test or active self
test); EOI = 0;
if = "11" device is in initialization phase or normal
mode and some errors are detected: acceleration
data are disregarded due to errors in device.
“0”: normal mode;
“1”: test mode
Will be set to '1' if write EOI = '1' attempt is made
with the device in +ve or -ve self-test (either CHX
or CHY).
“0” always
Loss of capacitor:
if = "0" then loss of capacitor is not detected
(correct behavior);
if = "1" then loss of capacitor is detected (wrong
behavior).
Note:
1.LOSS_CAP check is done during the power-up
stage (~400 μs after POR) only.
2.Recommended VDD ramp rate >1 V/ms
3.It is recommended that LOSS_CAP flag (and all
other hardware flags) be reconfirmed with soft
POR after power up (END_OF_PWRUP='1').
="1": end of power-up sequence; ready for self-
test.
Reset Active bit:
if = "0" then device is out of reset;
if = "1" then device has undergone a soft reset
sequence. Cleared by a read.
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